simulate_mti.do

spi接口的vhdl实现

vlib work

echo "Compiling Sink Top Gate Level Verilog"
vlog -quiet ../../../uart232_pl4_lite_snk_top.v

echo "Compiling Source Top Gate Level Verilog"
vlog -quiet ../../../uart232_pl4_lite_src_top.v

echo "Compiling FIFO Loopback Verilog"
vlog -quiet ../../example_design/pl4_lite_fifo_loopback_read.v \
            ../../example_design/pl4_lite_fifo_loopback_write.v \
            ../../example_design/pl4_lite_fifo_loopback.v



echo "Compiling PL4 LITE Wrapper Verilog"
vlog -quiet ../../example_design/uart232_top.v

echo "Compiling Test Bench Verilog"
vlog -quiet ../glbl.v
vlog -vlog95compat -quiet ../pl4_lite_clk_gen.v \
                          ../pl4_lite_startup.v \
                          ../pl4_lite_procedures.v \
                          ../pl4_lite_stimulus.v \
                          ../pl4_lite_testcase.v \
                          ../pl4_lite_data_monitor.v \
                          ../pl4_lite_status_monitor.v \
                          ../pl4_lite_demo_testbench.v

vsim -t ps -L simprims_ver -L unisims_ver work.pl4_lite_demo_testbench work.glbl
do wave_mti.do

# This simulation time of 8 us is selected as an example.  The simulation
# time may need to be extended for some core configurations so that both the
# Sink and Source cores will go in frame during simulation.
run 20000ns