pl4_lite_status_monitor.v

spi接口的vhdl实现

    FullVec      <= #`TFF {256{1'b1}};
    FullVecCnt   <= #`TFF 'b0;
    FullVecCnt_m <= #`TFF 'b0;
  end
  else if (SnkOof == 1)
  begin
    FullVecCnt   <= #`TFF 'b0;
    FullVecCnt_m <= #`TFF 'b0;
  end

  // Wait for the first valid status word
  else if ((FirstStat == 1) || ((FirstStat == 0) && (RStat != 2'b11)))
  begin

    // If it is framing set counters
    if ((FullVecCnt == 0) && (FullVecCnt_m == 0))
    begin
      FullVecCnt <= #`TFF 'b1;
      FullVecCnt_m <= #`TFF 'b1;
    end

    // If it is DIP2 reset counters
    else if ((FullVecCnt == SnkCalendar_Len + 2) &&
             (FullVecCnt_m == SnkCalendar_M + 1))
    begin
      FullVecCnt   <= 'b0;
      FullVecCnt_m <= 'b0;
    end

    // Otherwise it is valid status, so store it and update counters
    else
    begin
      FullVec[CalSeq[FullVecCnt - 1'b1]] <= #`TFF RStat[1];

      // If it is at the end of a calendar sequence, increment repetition 
      // counter, reset FullVecCnt.
      if ((FullVecCnt == SnkCalendar_Len + 1) &&
          (FullVecCnt_m < SnkCalendar_M + 1))
      begin
        FullVecCnt_m <= #`TFF FullVecCnt_m + 1'b1;
        FullVecCnt   <= #`TFF 'b1;
      end

      // Otherwise increment counter.
      else
        FullVecCnt <= #`TFF FullVecCnt + 1'b1;
    end
  end
end

/******************************************************************************
* Calculate DIP2 values
* This process calculates the DIP2 for RStat and compares it with what is
* actually received.
******************************************************************************/
always @(posedge RSClk or negedge Reset_n)
begin: calc_dip2
  if (!Reset_n)
    begin
      LenCnt               <= #`TFF 9'b1;
      MCnt                 <= #`TFF 1'b1;
      Dip2                 <= #`TFF 2'b00;
      FirstStat            <= #`TFF 1'b0;
      SnkDip2ErrRequest_d1 <= #`TFF 1'b0;
    end
  else
  begin
    SnkDip2ErrRequest_d1 <= #`TFF SnkDip2ErrRequest;

    // If the core is out of frame, reset DIP2 state
    if (SnkOof == 1)
    begin
      LenCnt <= #`TFF 9'b1;
      MCnt   <= #`TFF 1'b1;
      Dip2    <= #`TFF 2'b00;
      FirstStat <= #`TFF 1'b0;
    end

    // If the first status word has already been sent, or this is the first
    // status word after framing.  This ensures that you start calculating
    // the DIP2 value at the correct place.
    else if ((FirstStat == 1) || ((FirstStat == 0) && (RStat != 2'b11)))
    begin
      FirstStat <= #`TFF 1'b1;

      // If it is the first word of the sequence then send framing
      if ((LenCnt == 1'b0) && (MCnt == 1'b0))
      begin
        Dip2   <= #`TFF 2'b00;
        LenCnt <= #`TFF 1'b1;
        MCnt   <= #`TFF 1'b1;
      end

      // If it is the last status word then send the DIP2 value
      else if ((LenCnt == SnkCalendar_Len + 2) && (MCnt == SnkCalendar_M + 1))
      begin

        // Dip2 should equal the "next" value of Rstat. If it doesn't, then
        // process the error. The "next" value is calculated by inverting
        // and swapping the bits
        if ((Dip2[1] ^ 1'b1 == RStat[0]) && (Dip2[0] ^ 1'b1 == RStat[1]));
          // do nothing: dip2 match
   
        else
        begin
   
          // If the SnkDip2ErrReqFlag is set then a DIP2 error is expected
          if (SnkDip2ErrReqFlag == 1)
            $display("RStat Info: Expected DIP2 mismatch received.  SnkDip2ErrReqFlag = 1. %0d ps", $time); 
   
          //else
          //  $display("RStat Error: DIP2 error received. Expecting %d%d, recieved %b. SnkDip2ErrReqFlag = 0. %0d ps", Dip2[0] ^ 1'b1, Dip2[1] ^ 1'b1, RStat, $time); //  
        end
   
        LenCnt   <= #`TFF 1'b0;
        MCnt     <= #`TFF 1'b0;
        Dip2     <= #`TFF Dip2;

      end

      // Else it is a status word so just send it and calculate the new 
      // DIP2
      else 
      begin
        Dip2  <= #`TFF RStat ^ {Dip2[0], Dip2[1]};

        // Increment the MCnt (repetitions of the calendar) and reset the
        // LenCnt (length of the calendar) if you are at the end of the
        // calendar
        if ((LenCnt == SnkCalendar_Len + 1) && (MCnt < SnkCalendar_M + 1))
        begin
          MCnt   <= #`TFF (MCnt + 1);
          LenCnt <= #`TFF 1'b1;
        end

        // Otherwise just increment the LenCnt
        else
        begin
          LenCnt <= #`TFF LenCnt + 1;
        end
      end
    end
  end
end

/******************************************************************************
* Check SnkOof
* Checks the SnkOof signal.  If it is asserted, the flag SendFrame until
* you are not longer sending framing sequences.  If the Sink Core went out
* of frame after coming into frame then print message.  
******************************************************************************/
always @(posedge RSClk or negedge Reset_n)
begin: check_snkoof
  if (!Reset_n)
  begin
    SendFrame <= #`TFF 'b1;
  end
  else
  begin
    if (SnkOof == 1)
    begin
      if (SendFrame == 0)
        $display("RStat Info: Sink is out of frame. Expect TDat mismatches. %0d ps",$time);
      SendFrame <= #`TFF 1'b1;
    end
    else if (SendFrame == 1)
    begin
      if (RStat == 2'b11)
        SendFrame <= #`TFF 1'b1;
      else
        SendFrame <= #`TFF 1'b0;
    end
  end
end

/******************************************************************************
* Check SnkDip2ErrRequest
* Checks the SnkDip2ErrRequest signal.  If it is asserted, then it begins
* a count to four.  Once this delay is reached, then it flags
* SnkDip2ErrReqFlag.  As long as this signal is asserted, then expect DIP2
* errors on RStat.
******************************************************************************/
always @(posedge RSClk or negedge Reset_n)
begin: check_snkdip2errreq
  if (!Reset_n)
  begin
    SinceDip2ErrReq   <= #`TFF 'b0;
    SnkDip2ErrReqFlag <= #`TFF 1'b0;
  end
  begin

    // If SnkDip2ErrRequest is asserted, then start a count to 4.  Once you
    // reach for then set flag.
    if (SnkDip2ErrRequest == 1) 
    begin
      if ((SinceDip2ErrReq < 4) && (SnkDip2ErrReqFlag == 0))
      begin
        SinceDip2ErrReq <= #`TFF SinceDip2ErrReq + 1'b1;
      end
      else
      begin
        SinceDip2ErrReq <= #`TFF 'b0;
        SnkDip2ErrReqFlag <= #`TFF 1'b1;
      end
    end

    // If the flag is set but SnkDip2ErrRequest is no longer set, then
    // start a count to 8.  Once 8 is reached you can deassert
    // SnkDip2ErrReqFlag on the next framing word (Assuming that framing is
    // not being sent because the Source Core is out of frame). 
    else if (SnkDip2ErrReqFlag == 1)
    begin
      if (SinceDip2ErrReq < 9)
      begin
        SinceDip2ErrReq <= #`TFF SinceDip2ErrReq + 1'b1;
      end
      else
      begin
        if (RStat == 2'b11)
        begin
          if (SendFrame == 0)
          begin
            SinceDip2ErrReq   <= #`TFF 'b0;
            SnkDip2ErrReqFlag <= #`TFF 1'b0;
          end
        end
      end
    end

    // Case where SnkDip2ErrRequest was not asserted for 4 cycles, so
    // SnkDip2ErrReqFlag was not set.  There will be a DIP2 error on the
    // next framing word.
    else if ((SnkDip2ErrRequest == 0) && (SnkDip2ErrRequest_d1 == 1))
    begin
      SnkDip2ErrReqFlag <= #`TFF 1'b1;
    end
  end
end
endmodule