pl4_lite_status_monitor.v

spi接口的vhdl实现

/*****************************************************************************
* SPI-4.2 Status Monitor Module
******************************************************************************
*
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******************************************************************************
* Filename: pl4_lite_status_monitor.v
*
* Description: The status monitor checks the DIP2 value on RStat and
* compares it with the correct value.  It also notes if the Sink Core goes
* out of frame.  Lastly it creates the signal FullVec which is used by the
* control module.
* 
****************************************************************************/

`timescale 1ps/1ps

/****************************************************************************
* Library Declaration
****************************************************************************/
`include "../pl4_lite_testcase_pkg.v"

/****************************************************************************
* Module Declarations
****************************************************************************/
module pl4_lite_status_monitor(
  // System Signals
  Reset_n,
  UserClk,

  // Sink Core Signals
  RStat,
  RSClk,
  SnkOof,
  SnkAlmostFull_n,
  SnkDip2ErrRequest,

  // Source Core Singals
  SrcOof,
  SrcDip2Err,
  TStat,
  TSClk,

  // Static Configuration Signals
  SnkCalendar_Len,
  SnkCalendar_M,
  FifoAFMode,

  // Calendar Loading Signals
  CalWrEn_n,
  CalAddr,
  CalData, 

  // Outputs to Testcase
  FullVec,
  SnkInFrame
);

input       Reset_n;
input       UserClk;
input [1:0] RStat;
input       RSClk;
input       SnkOof;
input       SrcOof;
input       SnkAlmostFull_n;
input       SnkDip2ErrRequest;
input       SrcDip2Err;
input [1:0] TStat;
input       TSClk;
input [8:0] SnkCalendar_Len;
input [7:0] SnkCalendar_M;
input [1:0] FifoAFMode;
input       CalWrEn_n;
input [8:0] CalAddr;
input [7:0] CalData;
output [255:0] FullVec;
output      SnkInFrame;

wire        Reset_n;
wire        UserClk;
wire [1:0]  RStat;
wire        RSClk;
wire        SnkOof;
wire        SrcOof;
wire        SnkAlmostFull_n;
wire        SnkDip2ErrRequest;
wire        SrcDip2Err;
wire [1:0]  TStat;
wire        TSClk;
wire [8:0]  SnkCalendar_Len;
wire [7:0]  SnkCalendar_M;
wire [1:0]  FifoAFMode;
wire        CalWrEn_n;
wire [8:0]  CalAddr;
wire [7:0]  CalData;
reg  [255:0] FullVec;
wire        SnkInFrame;

/****************************************************************************
* Definistion of Ports
*****************************************************************************
* System Signals
*   Reset_n             :  Input reset (active low)
*   UserClk             :  Input clock for calendar programing
* Sink Core Signals
*   RStat               :  SPI-4.2 interface signals used for FIFO-Status-
*                          Channel flow control
*   RSClk               :  Source synchronous clock received with RStat.
*   SnkOof              :  Signal indicating that the Sink Core is out of
*                          frame.
*   SnkAlmostFull_n     :  Active low signal that indicates the Sink Core
*                          Fifo is almost full.  If FifoAFMode = '01' then
*                          the status monitor should expect satisfied on
*                          all channels.
* Source Core Signals
*   SrcOof              :  Signal indicating that the Source Core is our of
*                          frame.
*   SrcDip2Err          :  Signal that indicates that a DIP-2 parity error
*                          was detected on the Source FIFO status channel
*                          (TStat).
*   TStat               :  SPI-4.2 interface signal used for FIFO-Status-
*                          Channel flow control.
*   TSClk               :  Source synchronous clock received with TStat.
* Static Configuration Signals
*   SnkCalendar_Len     :  Length of one calendar sequence for the Sink
*                          Core
*   SnkCalendar_M       :  Number of times to repeat the calendar sequence
*                          before sending DIP2 and framing (Sink Core).
*   FifoAFMode          :  Indicates action that should be taken when the
*                          Sink Core fifo is almost full (SnkAlmostFull_n).
*                          '00': go out of frame
*                          '01': send satisfied on all channels
*                          '10' or '11': Continue normal operation
* Calendar Signals
*   CalWrEn_n           :  Active low signal that indicates there is valid
*                          data on CalData.
*   CalAddr             :  Position in the calendar sequence that the data
*                          is stored in.
*   CalData             :  Channel number that is to be stored in the
*                          calendar.
* Output Signals
*   FullVec             :  Bus that contains the status sent for every
*                          channel.  It is updated everytime TStat sends
*                          a new status value.
*   SnkInFrame          :  This signal is used by the control module to
*                          indicate that it can begin sending valid status.
*                          It is created from SnkOof.
****************************************************************************/

/****************************************************************************
* Signal Declarations
****************************************************************************/
reg  [15:0] FullVecCnt;         // Counter to track position for FullVec
reg  [15:0] FullVecCnt_m;       // Counter to track position in calendar for 
                                // FullVec.
reg  [7:0]  CalSeq [511:0];     // Sink Calendar Sequence
reg         SnkDip2ErrReqFlag;  // Flag to indicate that there will be a DIP2 
                                // error on RDat
reg  [3:0]  SinceDip2ErrReq;    // Counts the number of cycles since 
                                // SnkDip2ErrRequest was asserted or
                                // deasserted
reg         SendFrame;          // Indicates that the Sink Core is sending 
                                // framing
reg         SnkDip2ErrRequest_d1; // Registered version of SnkDip2ErrRequest

// Used for DIP2 calculation
reg [9:0] LenCnt;                // Keeps the position in the calendar sequence
reg [15:0] MCnt;                 // Counts the number of times through the 
                                 // calendar sequence
reg [1:0] Dip2;                  // Stires the DIP2 calculation
reg       FirstStat;             // Flag to indicate when first valid status 
                                 // word is sent

// Create SnkInFrame signal
assign SnkInFrame = ~SnkOof;

/*****************************************************************************
* Capture Sink Calendar
* Captures the calendar sequence that is loaded from the file so that the
* control module knows the sequence of the channels
*****************************************************************************/
always @(posedge UserClk)
  begin:capture_sink_calendar
    if (!CalWrEn_n)
     CalSeq [CalAddr] <= #`TFF CalData;
    else
     CalSeq [CalAddr] <= #`TFF CalSeq [CalAddr];
  end

/*****************************************************************************
* Create FullVec
* Create the FullVec signal which contatins whether each channel is full or 
* empty (1 for full).  This signal is used by the procedures module to
* determine whether to send data out
*****************************************************************************/
always @(posedge RSClk or negedge Reset_n)
begin:create_fullvec
  if (!Reset_n)
  begin