pl4_lite_startup.v

spi接口的vhdl实现

            begin
            State           <= #`TFF TDCLK_LCK;
            DCMReset_TDClk  <= #`TFF 1'b0;
            DCMReset_RDClk  <= #`TFF 1'b0;
            CountClear      <= #`TFF 1'b0;
            end
          Reset_n         <= #`TFF 1'b0;
          end

        /********************************************************************
        * State 3: RDCLK_RST
        * This state ensures that the DCM reset signal is asserted for
        * eight clock cycles.  After eight cycles of SPIClk DCMReset_RDClk
        * is deasserted and the state machine moves to the RDCLK_LCK state.
        ********************************************************************/
        RDCLK_RST:
          begin

          // Expand DCM Reset pulse duration to 8 clock cycles
          if (Count == 11'd7)
            begin
            State           <= #`TFF RDCLK_LCK;
            DCMReset_RDClk  <= #`TFF 1'b0;
            end
          else
            begin
            State           <= #`TFF RDCLK_RST;
            DCMReset_RDClk  <= #`TFF 1'b1;
            end
          DCMReset_TDClk  <= #`TFF 1'b0;
          CountClear      <= #`TFF 1'b0;
          Reset_n         <= #`TFF 1'b0;
          end

        /********************************************************************
        * State 4: RDCLK_LCK
        * This state waits for the Locked_RDClk signal from the core to be
        * asserted. If the Locked_RDClk signal is not asserted in 512 slock 
        * cycles of SPIClk, then the count is cleared, DCMReset_RDClk is 
        * asserted, and the state machine returns to the RDClk_RST state.
        ********************************************************************/
        RDCLK_LCK:
          begin

          // IF RDCLK DCM is locked, then go to next state
          if (Locked_RDClk == 1'b1)
            begin
              State           <= #`TFF CLKS_RDY;
              DCMReset_RDClk  <= #`TFF 1'b0;
              CountClear      <= #`TFF 1'b1;
            end

          // If counter has wrapped all the way around (512 cycles), then
          // reset the DCM again and go back to RDCLK_RST
          else if (Count == 11'd7)
            begin
            State           <= #`TFF RDCLK_RST;
            DCMReset_RDClk  <= #`TFF 1'b1;
            CountClear      <= #`TFF 1'b1;
            end

          // Else wait until counter expires
          else
            begin
            State            <= #`TFF RDCLK_LCK;
            DCMReset_RDClk   <= #`TFF 1'b0;
            CountClear       <= #`TFF 1'b0;
            end
          DCMReset_TDClk  <= #`TFF 1'b0;
          Reset_n         <= #`TFF 1'b0;
          end

        /*******************************************************************
        * State 5: CLKS_RDY
        * Once it is in this state all of the DCMs are locked.  Wait until
        * SnkClksRdy and SrcClksRdy are asserted before moving to the
        * RELEASE_RST state.
        *******************************************************************/
        CLKS_RDY:
          begin
          DCMReset_TDClk  <= #`TFF 1'b0;
          DCMReset_RDClk  <= #`TFF 1'b0;
          CountClear      <= #`TFF 1'b0;
          Reset_n         <= #`TFF 1'b0;
	   if (SnkClksRdy == 1'b1 && SrcClksRdy == 1'b1)
	    begin
             $display ("Sink and Source clocks are ready. %0d ps", $time); // rle
             State           <= #`TFF RELEASE_RST;
	    end
	   else if (Count == 11'd7)
	    begin 
	     State           <= #`TFF IDLE;
	    end 
	   else
	    begin 
	     State           <= #`TFF CLKS_RDY;
	    end 
          end


        /*******************************************************************
        * State 6: RELEASE_RST
        * Once it is in this state all of the DCMs are locked.  All of
        * the DCMReset signals are deasserted, the counter is cleared,
        * and the Reset_n signal is released.  The state machine will stay
        * in this state until the SysReset_n signal is asserted.
        *******************************************************************/
        RELEASE_RST:
          begin
          DCMReset_TDClk  <= #`TFF 1'b0;
          DCMReset_RDClk  <= #`TFF 1'b0;
          CountClear      <= #`TFF 1'b1;
          Reset_n         <= #`TFF 1'b1;
          State           <= #`TFF RELEASE_RST;
          end

        /*******************************************************************
        * Error and Default States
        * In the error or default states the counter is reset and the
        * state machine returns to the IDLE state.
        *******************************************************************/
        default:
          begin
          State           <= #`TFF IDLE;
          DCMReset_TDClk  <= #`TFF 1'b0;
          DCMReset_RDClk  <= #`TFF 1'b0;
          CountClear      <= #`TFF 1'b1;
          Reset_n         <= #`TFF 1'b0;
          end
        endcase
      end
  end

/***************************************************************************
* Sink Calendar
****************************************************************************
* Load Data Process: Reads the Sink calendar data from text file
* Reads the Calendar data from the file defined in `SNK_CAL_DATA.  It also
* sets the length of the Calendar SnkCalendar_Len
***************************************************************************/
always @(posedge SnkStatClk or negedge Reset_n)
begin: load_snk_data
  if (!Reset_n)
    begin
    $readmemh(SnkCalDataFile, DataOut);
    AddrLen <= #`TFF SnkCalendar_Len;
    end
end

/***************************************************************************
* Sink Calendar Programing complete
* Asserts the CalProgCom signal when the Sink Calendar has been completely
* programmed.  It waits for the SnkCalWrEn_n to transition from low to high
* before asserting the CalProgCom signal.
***************************************************************************/
always @(posedge SnkStatClk or negedge Reset_n)
begin: Cal_Complete
  if (!Reset_n)
    begin
    CalProgCom <= #`TFF 1'b0;
    CalWrEnOn <= #`TFF 1'b0;
    end

  // If SnkCalWrEn_n = 0 then the calendar is programming, so set the
  // CalWrEnOn flag
  else if (SnkCalWrEn_n == 0)
    CalWrEnOn <= #`TFF 1'b1;

  // If SnkCalWrEn_n = 1 and CalWrEnOn = 1 then the calendar has already
  // been programmed, so set the CalProgCom flag
  else if (SnkCalWrEn_n == 1 && CalWrEnOn == 1)
    CalProgCom <= #`TFF 1'b1;
  else
    CalProgCom <= #`TFF 1'b0;
end

/***************************************************************************
* Sink Calendar Write Enable
* Sets the Calendar write enable signal (SnkCalWrEn_n).  It is asserted
* when the DCMs are locked (Reset_n is high) and the address counter
* (AddrCnt) is above zero
***************************************************************************/
always @(posedge SnkStatClk or negedge Reset_n)
begin: CalWr
  if (!Reset_n)
  begin
    SnkCalWrEn_n <= #`TFF 1'b1;
    EndWrEn   <= #`TFF 1'b0;
  end
  else if ((SnkCalendar_Len == 0) && (EndWrEn == 0))
  begin
    SnkCalWrEn_n <= #`TFF 1'b0;
    EndWrEn   <= #`TFF 1'b1;
  end
  else if (AddrCnt > 0)
    SnkCalWrEn_n <= #`TFF 1'b0;
  else
    SnkCalWrEn_n <= #`TFF 1'b1;
end

/***************************************************************************
* Sink Calendar Address Counter
* Sets the address of the location in the DataOut array that will be
* programmed next.  This is between AddrLen and zero
***************************************************************************/
always @(posedge SnkStatClk or negedge Reset_n)
begin: addcnt
  if (!Reset_n)
    AddrCnt <= #`TFF AddrLen;
  else if (SnkCalWrEn_n == 0 && AddrCnt > 0)
    AddrCnt <= #`TFF (AddrCnt - 1);
  else
    AddrCnt <= #`TFF AddrCnt;
end

/***************************************************************************
* Process for Sink Enable
* Assets the SnkEn signal when the Reset is deasserted (the DCMs are
* locked) and the Calendar Programming is complete
***************************************************************************/
always @(negedge Reset_n or posedge SnkStatClk)
begin:snk_en
  if (!Reset_n)
    SnkEn <= #`TFF 1'b0;
  else if (CalProgCom == 1'b1)
    SnkEn <= #`TFF 1'b1;
  else
    SnkEn <= #`TFF 1'b0;
end

//Source Calendar
/***************************************************************************
* Load Data Process: Reads the Source calendar data from text file
* Reads the Calendar data from the file defined in `SRC_CAL_DATA.  It also
* sets the length of the Calendar SrcCalendar_Len
***************************************************************************/
always @(posedge SrcStatClk or negedge Reset_n)
begin: load_src_data
  if (!Reset_n)
    begin
    $readmemh(SrcCalDataFile, SrcDataOut);
    SrcAddrLen <= #`TFF SrcCalendar_Len;
    end
end

/***************************************************************************
* Source Calendar Programing complete
* Asserts the SrcCalProgCom signal when the Calendar has been completely
* programmed.  It waits for the SrcCalWrEn_n to transition from low to high
* before asserting the SrcCalProgCom signal.
***************************************************************************/
always @(posedge SrcStatClk or negedge Reset_n)
begin: src_Cal_Complete
  if (!Reset_n)
    begin
    SrcCalProgCom <= #`TFF 1'b0;
    SrcCalWrEnOn <= #`TFF 1'b0;
    end

  // If SrcCalWrEn_n = 0 then the calendar is programming, so set the
  // SrcCalWrEnOn flag
  else if (SrcCalWrEn_n == 0)
    SrcCalWrEnOn <= #`TFF 1'b1;

  // If SrcCalWrEn_n = 1 and SrcCalWrEnOn = 1 then the calendar has already
  // been programmed, so set the SrcCalProgCom flag
  else if (SrcCalWrEn_n == 1 && SrcCalWrEnOn == 1)
    SrcCalProgCom <= #`TFF 1'b1;
  else
    SrcCalProgCom <= #`TFF 1'b0;
end

/***************************************************************************
* Source Calendar Write Enable
* Sets the Source Calendar write enable signal (SrcCalWrEn_n).  It is asserted
* when the DCMs are locked (Reset_n is high) and the address counter
* (SrcAddrCnt) is above zero
***************************************************************************/
always @(posedge SrcStatClk or negedge Reset_n)
begin: src_CalWr
  if (!Reset_n)
  begin
    SrcCalWrEn_n <= #`TFF 1'b1;
    SrcEndWrEn   <= #`TFF 1'b0;
  end
  else if ((SrcCalendar_Len == 0) && (SrcEndWrEn == 0))
  begin
    SrcCalWrEn_n <= #`TFF 1'b0;
    SrcEndWrEn   <= #`TFF 1'b1;
  end
  else if (SrcAddrCnt > 0)
    SrcCalWrEn_n <= #`TFF 1'b0;
  else
    SrcCalWrEn_n <= #`TFF 1'b1;
end

/***************************************************************************
* Source Calendar Address Counter
* Sets the address of the location in the SrcDataOut array that will be
* programmed next.  This is between SrcAddrLen and zero
***************************************************************************/
always @(posedge SrcStatClk or negedge Reset_n)
begin: src_addcnt
  if (!Reset_n)
    SrcAddrCnt <= #`TFF SrcAddrLen;
  else if (SrcCalWrEn_n == 0 && SrcAddrCnt > 0)
    SrcAddrCnt <= #`TFF (SrcAddrCnt - 1);
  else
    SrcAddrCnt <= #`TFF SrcAddrCnt;
end

/***************************************************************************
* Process for Source Enable
* Asserts SrcEn when the Reset is deasserted (the DCMs are locked) and
* the Calendar Programming is complete
***************************************************************************/
always @(negedge Reset_n or posedge SrcStatClk)
begin:src_en
  if (!Reset_n)
    SrcEn <= #`TFF 1'b0;
  else if (SrcCalProgCom == 1'b1)
    SrcEn <= #`TFF 1'b1;
  else
    SrcEn <= #`TFF 1'b0;
end

/****************************************************************************
* Drive Outputs
****************************************************************************/

assign SnkCalData   = DataOut[AddrCnt];
assign SnkCalAddr   = AddrCnt;
assign SrcCalData   = SrcDataOut[SrcAddrCnt];
assign SrcCalAddr   = SrcAddrCnt;

endmodule