pl4_lite_startup.v

spi接口的vhdl实现

/*****************************************************************************
* SPI-4.2 Startup
* DCM startup and Calendar Loader
******************************************************************************
*
*  Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
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*  grants you a license to use this text/file solely for
*  design, simulation, implementation and creation of
*  design files limited to Xilinx devices or technologies.
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*  prohibited and immediately terminates your license unless
*  covered by a separate agreement.
*
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*  solutions for Xilinx devices, with no obligation on the
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*  code, or information as one possible implementation of
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*
*  This copyright and support notice must be retained as part
*  of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc.
*  All rights reserved.
*
******************************************************************************
* Filename: pl4_lite_startup.v
*
* Description: Sets the proper startup sequence for the DCMs.  This will
* allow proper initialization of the clocking scheme for the entire system.
* After this initialization is complete the reset is released and the
* calendar is programed.  Once the calendar programming is complete the
* cores are enabled.
*
****************************************************************************/

`timescale 1ps/1ps

/****************************************************************************
* Library Declarations
****************************************************************************/
`include "../pl4_lite_testcase_pkg.v"

/****************************************************************************
* Module Declarations
****************************************************************************/
module pl4_lite_startup (
  // System Signals
  SysReset_n,
  SPIClk,
  UserClk,

  // SPI4.2 Sink DCM Status
  DCMReset_RDClk,
  Locked_RDClk,
  SnkClksRdy,

  // SPI4.2 Source DCM Status
  DCMReset_TDClk,
  Locked_TDClk,
  SrcClksRdy,
  Reset_n,

  // Calendar Programming
  SrcCalendar_Len,
  SnkCalendar_Len,
  SnkStatClk,
  SrcStatClk,
  SrcCalWrEn_n,
  SrcCalAddr,
  SrcCalData,
  SnkCalWrEn_n,
  SnkCalAddr,
  SnkCalData,

  // Sink and Source Core enables
  SnkEn,
  SrcEn
);

input           SysReset_n;
input           SPIClk;
input           UserClk;
output          DCMReset_RDClk;
input           Locked_RDClk;
input           SnkClksRdy; 
output          DCMReset_TDClk;
input           Locked_TDClk;
input           SrcClksRdy; 
output          Reset_n;
input  [8:0]    SnkCalendar_Len;
input  [8:0]    SrcCalendar_Len;
input           SnkStatClk;
input           SrcStatClk;
output          SrcCalWrEn_n;
output [8:0]    SrcCalAddr;
output [7:0]    SrcCalData;
output          SnkCalWrEn_n;
output [8:0]    SnkCalAddr;
output [7:0]    SnkCalData;
output          SnkEn;
output          SrcEn;

reg             DCMReset_RDClk;
wire            Locked_RDClk;
wire            SnkClksRdy; 
reg             DCMReset_TDClk;
wire            Locked_TDClk;
wire            SrcClksRdy; 
reg             Reset_n;
wire    [8:0]   SnkCalendar_Len;
wire    [8:0]   SrcCalendar_Len;
wire            SnkStatClk;
wire            SrcStatClk;
reg             SrcCalWrEn_n;
wire    [8:0]   SrcCalAddr;
wire    [7:0]   SrcCalData;
reg             SnkCalWrEn_n;
wire    [8:0]   SnkCalAddr;
wire    [7:0]   SnkCalData;
reg             SnkEn;
reg             SrcEn;

/****************************************************************************
* Definition of Ports:
*****************************************************************************
* System Signals
*   SysReset_n                  :  Input Reset (active low)
*   SPIClk                      :  SPI Interface Clock
*   DCMReset_RDClk              :  RDClk DCM Reset (active high)
*   Locked_RDClk                :  RDClk DCM Locked signal (active high)
*   DCMReset_TDClk              :  TDClk DCM Reset (active high)
*   Locked_TDClk                :  TDClk DcM Locked signal (active high)
*   Reset_n                     :  System Level Reset indicating all DCMs are
*                                  locked
*   SnkStatClk                  :  Sink Calendar Programming Clock
*   SrcStatClk                  :  Source Calendar Programming Clock
*   SrcCalWrEn_n                :  Signal indicating that the calendar is
*                                  writing data to the Source
*   SrcCalAddr                  :  Address to write the Source calendar data to
*   SrcCalData                  :  Signal containing the calendar data that
*                                  is to be written the the Source Core
*   SnkCalWrEn_n                :  Signal indicating that the calendar is
*                                  writing data to the Sink
*   SnkCalAddr                  :  Address to write the Sink calendar data to
*   SnkCalData                  :  Signal containing the calendar data that
*                                  is to be written the the Sink Core
*   SnkEn                       :  Enable signal for the SPI-4.2 sink core
*   srcEn                       :  Enable signal for the SPI-4.2 source core
***************************************************************************/

/***************************************************************************
* Parameter Declarations
***************************************************************************/

/***************************************************************************
* State Machine Parameter Declarations
***************************************************************************/

// FSM State
parameter IDLE          = 7'b0000001;
parameter TDCLK_RST     = 7'b0000010;
parameter TDCLK_LCK     = 7'b0000100;
parameter RDCLK_RST     = 7'b0001000;
parameter RDCLK_LCK     = 7'b0010000;
parameter CLKS_RDY      = 7'b0100000;
parameter RELEASE_RST   = 7'b1000000;

// Data files
parameter SnkCalDataFile = "../snk_calendar.dat";
parameter SrcCalDataFile = "../src_calendar.dat";

/***************************************************************************
* Signal Declaration
***************************************************************************/
reg [8:0] State;
reg       CountClear;
reg [10:0] Count;
reg [2:0] StateSnk;
reg [7:0] WaitCount;
reg [8:0] SrcAddrLen;
reg [8:0] SrcAddrCnt;
reg [7:0] SrcDataOut [1023:0];
reg       SrcCalProgCom;
reg       SrcCalWrEnOn;
reg       SrcEndWrEn;
reg [8:0] AddrLen;
reg [8:0] AddrCnt;
reg [7:0] DataOut [1023:0];
reg       CalProgCom;
reg       CalWrEnOn;
reg       EndWrEn;

/***************************************************************************
* Initialize all outputs and internal signals
***************************************************************************/
initial
begin
  State           <= IDLE;
  DCMReset_TDClk  <= 1'b0;
  DCMReset_RDClk  <= 1'b0;
  CountClear      <= 1'b1;
  Count           <= 11'b0;
  Reset_n         <= 1'b0;
end

/***************************************************************************
* Counter tied to SPIClk
* The counter counts up to 2047 and is used to move between states in the
* DCM startup state machine.  The state machine moves from reset to locked
* states after an 8 count and from locked back to reset after a 2047 count
***************************************************************************/
always @(posedge SPIClk or negedge SysReset_n)
  begin:counter
    if (!SysReset_n)
      Count <= 11'b0;
    else if (CountClear == 1)
      Count <= 11'b0;
    else
      Count <= Count + 1;
  end

/****************************************************************************
* DCM Startup State Machine Process
* Ensures each DCM is locked before releasing the Reset_n signal
****************************************************************************/
always @(negedge SysReset_n or posedge SPIClk)
  begin: rst_fsm
    if (!SysReset_n)
      begin
      State          <= #`TFF IDLE;
      DCMReset_TDClk <= #`TFF 1'b0;
      DCMReset_RDClk <= #`TFF 1'b0;
      CountClear     <= #`TFF 1'b1;
      Reset_n        <= #`TFF 1'b0;
      end
    else
      begin
        case (State)

        /********************************************************************
        * State 0: IDLE
        * Initial State after reset.  The counter is reset and the
        * DCMReset_TDClk signal is asserted.  This signal resets the TDClk
        * DCM in the core.  The state machine moves to the TDCLK_RST state
        * after IDLE.
        ********************************************************************/
        IDLE:
          begin
            State           <= #`TFF TDCLK_RST;
            DCMReset_TDClk  <= #`TFF 1'b1;
            DCMReset_RDClk  <= #`TFF 1'b0;
            CountClear      <= #`TFF 1'b1;
            Reset_n         <= #`TFF 1'b0;
	    $display ("Timing checks are not valid. %0d ps", $time);
          end

        /********************************************************************
        * State 1: TDCLK_RST
        * This state ensures that the DCM reset signal is asserted for
        * eight clock cycles.  After eight cycles of SPIClk DCMReset_TDClk
        * is deasserted and the state machine moves to the TDCLK_LCK state.
        ********************************************************************/
        TDCLK_RST:
          begin
          // Expand DCM Reset pulse duration to 8 clock cycles
          if (Count == 11'd7)
            begin
            State           <= #`TFF TDCLK_LCK;
            DCMReset_TDClk  <= #`TFF 1'b0;
            end
          else
            begin
            State           <= #`TFF TDCLK_RST;
            DCMReset_TDClk  <= #`TFF 1'b1;
            end
          DCMReset_RDClk  <= #`TFF 1'b0;
          CountClear      <= #`TFF 1'b0;
          Reset_n         <= #`TFF 1'b0;
          end

        /********************************************************************
        * State 2: TDCLK_LCK
        * This state waits for the Locked_TDClk signal from the core to be
        * asserted.  Once this happens it resets the counter and sets
        * DCMReset_RDClk to 1 before moving onto the RDCLK_RST state.  If
        * the Locked_TDClk signal is not asserted in 512 slock cycles of
        * SPIClk, then the count is cleared, DCMReset_TDClk is asserted,
        * and the state machine returns to the TDClk_RST state.
        ********************************************************************/
        TDCLK_LCK:
          begin

          // if TDCLK DCM is locked, then go to next state
          if (Locked_TDClk == 1'b1)
            begin
            State           <= #`TFF RDCLK_RST;
            DCMReset_RDClk  <= #`TFF 1'b1;
            DCMReset_TDClk  <= #`TFF 1'b0;
            CountClear      <= #`TFF 1'b1;
            end

          // if counter has wrapped all the way around (512 cycles), then
          // reset the DCM again and go back to TDCLK_RST
          else if (Count == 11'd7)
            begin
            State           <= #`TFF TDCLK_RST;
            DCMReset_TDClk  <= #`TFF 1'b1;
            DCMReset_RDClk  <= #`TFF 1'b0;
            CountClear      <= #`TFF 1'b1;
            end

          // Else wait for the DCM to lock or the counter to expire
          else