pl4_lite_testcase.v

spi接口的vhdl实现

/*****************************************************************************
* SPI-4.2 Testcase
******************************************************************************
*
*  Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
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*  grants you a license to use this text/file solely for
*  design, simulation, implementation and creation of
*  design files limited to Xilinx devices or technologies.
*  Use with non-Xilinx devices or technologies is expressly
*  prohibited and immediately terminates your license unless
*  covered by a separate agreement.
*
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*  solutions for Xilinx devices, with no obligation on the
*  part of Xilinx to provide support. By providing this design,
*  code, or information as one possible implementation of
*  this feature, application or standard, Xilinx is making no
*  representation that this implementation is free from any
*  claims of infringement. You are responsible for obtaining
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*
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*
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*
*  This copyright and support notice must be retained as part
*  of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc.
*  All rights reserved.
*
*
******************************************************************************
* Filename: pl4_lite_testcase.v
*
* Description:  This module can be modified to vary the operation of the
* Demonstration Testbench.  It simulates a PL4-Phy device by transmitting
* data and status. By default the data is a specified sequence.  The status
* is randomly generated.  The module also contains all static configuration 
* signals for the SPI-4.2 core.  
*
******************************************************************************
* Structure: pl4_lite_testcase.v
*
*
*****************************************************************************/
`timescale 1ps/1ps

/*****************************************************************************
* Library Declarations
*****************************************************************************/
`include "../pl4_lite_testcase_pkg.v"

/*****************************************************************************
* Constant Declarations
*****************************************************************************/

/*****************************************************************************
* Module Declarations
*****************************************************************************/
module pl4_lite_testcase(
  //System Signals
  SysReset_n,
  Reset_n,
  RDClk2x,
  SysClk,
  TSClk,

  //Control module signals
  TCStat,
  TCChan,
  TCCtl,
  TCDat,
  TCIdleRequest,
  TCTrainingRequest,
  TCSnkDip2ErrRequest,
  CtlFull,
  FFWriteEn,
  SopErr,
  GetStatus,
  GetStatusChan,
  TCDIP2Request,
  TCComplete,   

  //Monitor signals
  SnkInFrame,
  SrcInFrame,
  FullVec,

  //Core signals
  SnkAlmostFull_n, // rle
  SnkOof,
  SrcOof,
  SnkEn,
  SrcEn,
  SnkFifoReset_n,
  SrcFifoReset_n
);

/*****************************************************************************
* Parameter Declarations
*****************************************************************************/
parameter      CheckRStat  = 'd0;
parameter      DataType    = 'b01;
parameter      NumLinks    = 'd16;
parameter      RandomSeed  = 'd5431;
parameter      RDClkPeriod = 2860;

output SysReset_n;
input  Reset_n;
input  RDClk2x;
input  SysClk;
input  TSClk;

//Control module signals
output [1:0]  TCStat;
output [15:0] TCChan;
output        TCCtl;
output [17:0] TCDat;
output        TCIdleRequest;
output        TCTrainingRequest;
output        TCSnkDip2ErrRequest;
input         CtlFull;
output        FFWriteEn;
output        SopErr;
input  [1:0]  GetStatus;
output [7:0]  GetStatusChan;
output        TCDIP2Request;
output        TCComplete;

//Monitor signals
input         SnkInFrame;
input         SrcInFrame;
input [255:0] FullVec;

//Core signals
input        SnkAlmostFull_n; // rle
input        SnkOof;
input        SrcOof;
output       SnkEn;
output       SrcEn;
output       SnkFifoReset_n;
output       SrcFifoReset_n;

reg   SysReset_n;
wire  Reset_n;
wire  RDClk2x;
wire  SysClk;
wire  TSClk;


//Control module signals
wire [1:0]   TCStat;
wire [15:0] TCChan;
wire         TCCtl;
wire [17:0]  TCDat;
reg          TCIdleRequest;
reg          TCTrainingRequest;
reg          TCSnkDip2ErrRequest;
wire         CtlFull;
wire         FFWriteEn;
wire         SopErr;
wire [1:0]   GetStatus;
wire [7:0]   GetStatusChan;
reg          TCDIP2Request;
reg 	     TCComplete;


wire         SnkAlmostFull_n; // rle
reg 	     SnkEn;
reg 	     SrcEn;
reg          SnkFifoReset_n;
reg          SrcFifoReset_n;
  

  //Monitor signals
wire         SnkInFrame;
wire         SrcInFrame;
wire [255:0] FullVec;

/*****************************************************************************
* Definition of Ports:
******************************************************************************
* System Signals
*   Reset_n                :  Input Reset (active low)
*   RDClk2x                :  clock used for the creation of data to be sent
*                             to the core (default 800Mhz)
*   SysClk                 :  System Clock (default 400Mhz)
*   TSClk                  :  Input clock from the clock generator used to
*                             create the status signal
*   CoreInitialized        :  Signal from the startup module that indicates
*                             that the core is initialized
* Testcase Signals
*   TCStat                 :  Status signal from the testcase module
*   TCChan                 :  The channel number to write TCStat
*   TCCtl                  :  Control Signal from the testcase module
*   TCDat                  :  Data bus from the testcase module
*   TCIdleRequest          :  Signal from the testcase module indicating the
*                             control module should send an idle request to 
*                             the core
*   TCTrainingRequest      :  Signal from the testcase module indicating the
*                             control module should send a training request to
*                             the core
*   TCSnkDip2ErrRequest    :  Signal from the testcase module that drives the
*                             SnkDip2ErrRequest signal.
*   CtlFull                :  Signal from the control module to the testcase
*                             module indicating that its buffers are full
*                             and the testcase module should stop sending dat
*   FFWriteEn              :  Indicates that valid data is being passed
*                             from the testcase module to the control module
* Monitor Signals
*   SnkInFrame             :  Signal from the monitor block that indicates that
*                             the Sink core is in frame
*   SrcInFrame             :  Signal from the monitor block that indicates that 
*                             the Source core is in frame
*   FullVec                :  A 256-bit vector which contains whether each 
*                             channel is full or not
******************************************************************************
* Definition of Parameters:
******************************************************************************
*   CheckRStat             :  Whether to check fullness of channel before
*                             beginning to send a packet
*   DataType               :  Whether to send incrementing, random, or file
*                             data
*   NumLinks               :  Number of channels
*   RandomSeed             :  Seed for random number generator
*   RDClkPeriod            :  Period of RDClk
*****************************************************************************/
 
/*****************************************************************************
* Signal Declarations
*****************************************************************************/
reg        TCDIP4Request;  //When asserted the testcase will send a DIP4 error 
                           //for that packet 
reg [7:0]  Chan;           //Contains the channel status will be sent to
reg [1:0]  Status;         //Contains that status value that will be sent out
reg [3:0]  GetChan;        //Contatins the channel to get status from
reg        GetInitial;     //When asserted the testcase will get status on
                           //channel GetChan
reg [15:0] Rand16;         //Used to create a random 16-bit value
reg [1:0]  RandStatus;     //Used to create a random status value
reg [2:0]  RandTrain;      //Used to create random training

//The following are used to randomly toggle request signals
reg [4:0]  RandIdleRequest;  
reg [4:0]  RandTrainingRequest;
reg [4:0]  RandDIP4Request;
reg [4:0]  RandDIP2Request;
reg [4:0]  RandSnkDip2ErrRequest;

//The counters are used to determin how long each signal is active
reg [3:0]  IdleRequestCnt;
reg [3:0]  TrainingRequestCnt;
reg [3:0]  DIP4RequestCnt;
reg [3:0]  DIP2RequestCnt;
reg [3:0]  SnkDip2ErrRequestCnt;

//Emulate the GSR (See answers 5009 and 1078 in the
//Xilinx Answers Database for more information)
wire GSR = glbl.GSR;

//Random number seed
integer    IntSeed;

//Temporary variable
integer    i;

/*****************************************************************************
* Instantiate Procedures Module
*****************************************************************************/
pl4_lite_procedures tasks (
  .RDat          (TCDat),
  .RCtl          (TCCtl),
  .RDClk2x       (RDClk2x),
  .Stat          (TCStat),
  .Chan          (TCChan),
  .TSClk         (TSClk),
  .FFWriteEn     (FFWriteEn),
  .SopErr        (SopErr),
  .TCDIP4Request (TCDIP4Request),
  .GetStatusChan (GetStatusChan),
  .FullVec       (FullVec),
  .FFFull        (CtlFull),
  .SnkAlmostFull_n (SnkAlmostFull_n) , // rle
  .CheckRStat    (CheckRStat),
  .RandomSeed    (RandomSeed)
);


/*****************************************************************************
* Initial Conditions
*****************************************************************************/
initial
begin
  TCIdleRequest       = 0;
  TCTrainingRequest   = 0;
  TCSnkDip2ErrRequest = 0;
  TCDIP4Request       = 0;
  TCDIP2Request       = 0;
  TCComplete          = 0;
  SnkEn               = 1;
  SrcEn               = 1;
  SnkFifoReset_n      = 1;
  SrcFifoReset_n      = 1;
  SysReset_n          = 0;
  wait (GSR == 0);
  SysReset_n = 1;
  tasks.reset;
  wait (Reset_n == 1);
  @ (posedge RDClk2x);

  if (CheckRStat == 1)
  begin
    wait (FullVec != {256{1'b1}});
    @ (posedge RDClk2x);
  end

  //**************************************************************************
  // Sends out randomized data, idles, or training.
  //**************************************************************************
  for (i=0; i<25; i=i+1)
  begin
    IntSeed = RandomSeed + $time;
    RandTrain = {$random(IntSeed)} % 4;
    
    //Sends a random sized complete packet to a random channel
    IntSeed = RandomSeed + $time;
    tasks.send_packet({$random(IntSeed)} % (NumLinks), ($random(IntSeed) % 255) + 1'b1);

    //Sends a random number of credits to a random channel.  The packet always
    //contains an SOP, no EOP, and will be a multiple of 16 bytes (1 credit)
    IntSeed = RandomSeed + $time;
    tasks.send_user_data(1,0,0,{$random(IntSeed)} % (NumLinks), (($random(IntSeed) % 6) + 1'b1)*16);

    //Sends a random number of idles to the Sink Core
    IntSeed = RandomSeed + $time;
    tasks.send_idles(({$random(IntSeed)} % 10) + 1);

    //Sends a random complete packet to a random channel.  The packet always
    //contains an SOP, EOP, and an EOP Abort.
    IntSeed = RandomSeed + $time;
    tasks.send_user_data(1,1,1,{$random(IntSeed)} % (NumLinks), (($random(IntSeed) % 255) + 1'b1));

    //Randomly send 5 training patterns to the sink core
    if (RandTrain == 2)
     begin      
      tasks.send_training(5);
     end
   
    //Sends a small (4 byte) packet to a random channel
    IntSeed = RandomSeed + $time;
    tasks.send_packet({$random(IntSeed)} % (NumLinks),4);
    
    //Sends 6 idles to the Sink Core
    tasks.send_idles(6);

    //Sends 1 credit (16 bytes) to channel 4.  The packet contains an SOP, no
    //EOP and no EOP Abort
    tasks.send_user_data(1,0,0,4,16);
   
    wait (SnkOof == 1'b0 && SrcOof == 1'b0);  

  end
  
  //Complete last packet
  tasks.send_user_data(0,1,0,4,16);
 
  TCComplete = 1;

end

//******************************************************************************
// Send Status
//******************************************************************************
// Cycles through the calendar sequence and sends a random value for each
// channel (except channel 10 which is always satisfied) to the Source core.
// Also reads status from the backend interface.
//******************************************************************************
initial
begin
  Status     = 2'b01;
  Chan       =  'b0;
  RandStatus = 2'b00;
  GetChan    = 'b0;
  GetInitial = 'b0;

  wait (SrcInFrame == 1);
  @(posedge TSClk);
  forever
    begin
    tasks.send_status(Chan, Status);
    if (Chan == NumLinks - 1)
      GetInitial = 'b1;

    if (Chan == 10)
      Status <= #`TFF 2'b10;
    else
    begin
      IntSeed = RandomSeed + $time;
      Rand16 = $random(IntSeed);
      RandStatus = Rand16 % 3;
      if (RandStatus == 0)
        Status <= #`TFF 2'b00;
      else if (RandStatus == 1)
        Status <= #`TFF 2'b01;
      else if (RandStatus == 2)
        Status <= #`TFF 2'b10;
      else
        $display("RandStatus out of range: %d at time %d", RandStatus, $time);
    end

    Chan <= #`TFF (Chan + 1) % NumLinks;

    if (GetInitial == 'b1)
    begin
      tasks.get_status(GetChan);
      GetChan <= #`TFF (GetChan + 1) % NumLinks;
    end

    @ (posedge TSClk);

  end
end


endmodule