pl4_lite_procedures.v

spi接口的vhdl实现

/*****************************************************************************
* SPI-4.2 Procedures Module
******************************************************************************
*
*  Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
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*  All rights reserved.
*
******************************************************************************
* Filename: pl4_lite_procedures.v
*
* Description: The procedures module contains all of the public and private
* tasks that are used in the Demonstration Testbench.  
*
****************************************************************************/

`timescale 1ps/1ps

`include "../pl4_lite_testcase_pkg.v"

module pl4_lite_procedures (
  RDat,
  RCtl,
  RDClk2x,
  SopErr,
  TCDIP4Request,
  Stat,
  Chan,
  TSClk,
  FFWriteEn,
  GetStatusChan,
  FFFull,
  FullVec,
  SnkAlmostFull_n, // 
  CheckRStat,
  RandomSeed
);

output [17:0] RDat;
output        RCtl;
input         RDClk2x;
output        SopErr;
input         TCDIP4Request;
output [1:0]  Stat;
output [15:0] Chan;
input         TSClk;
output        FFWriteEn;
output [7:0]  GetStatusChan;
input         FFFull;
input  [255:0] FullVec;
input         CheckRStat;
input  [31:0] RandomSeed;
input         SnkAlmostFull_n ; // 

reg    [17:0] RDat;
reg           RCtl;
wire          RDClk2x;
reg           SopErr;
wire          TCDIP4Request;
reg    [1:0]  Stat;
reg    [15:0] Chan;
wire          TSClk;
reg           FFWriteEn;
reg    [7:0]  GetStatusChan;
wire          FFFull;
wire   [255:0] FullVec;
wire           SnkAlmostFull_n;

/*****************************************************************************
* Definition of Ports
******************************************************************************
*   RDat                 : 18 bit data that is sent out of the procedures
*                          module.  The first 16 bits are data, bit 17
*                          contains whether or not the data should have
*                          a dip4 error, and bit 18 is reserved.
*   RCtl                 : Output control signal
*   RDClk2x              : Clock used for the creation of data to be sent
*                          to the core (Default 800Mhz)
*   SopErr               : Output that indicates there is a wanted SOP
*                          spacing error in the data.  Used to ensure that
*                          the control block does not insert idles
*   TCDIP4Request        : Indicates that a DIP4 error is wanted on RDat
*   Stat                 : 2 bit status line
*   Chan                 : Channel to send status
*   TSClk                : Clock used for the generation of status (Default
*                          100Mhz)
*   FFWriteEn            : Indicates that data is being written to the
*                          control block and should be stored in the fifo.
*   GetStatusChan        : Indicates the channel that the user wants to see
*                          the status of
*   FullVec              : Contains the status (full-1 or empty-0) of all
*                          channels.  Used to not send data to a full
*                          channel if CheckRStat is set to 1
*****************************************************************************/

/*****************************************************************************
* Signal Declarations
*****************************************************************************/
reg    [15:0] DataOut [1023:0]; //Stores data to be written out if 
                                //DATA_TYPE = 2'b10 or 2'b00
reg    [9:0]  DataCnt;          //Counter for DataOut
reg    [9:0]  FileLength;       //The length of the data file read
reg    [9:0]  k;                //Counter used for initialization
reg    [9:0]  m;                //Counter used for initialization

/*****************************************************************************
* Load the Data from a file if the DATA_TYPE constant is set to 10
* Initialize every channels data to zero if DATA_TYPE is 00 (increment
* data)
*****************************************************************************/
initial
begin
  DataCnt = 0;
  SopErr  = 0;
  FileLength = 0;
  if (`DATA_TYPE == 2'b10)
  begin
    for (k = 0; k < 1023; k = k + 1)
    begin
      DataOut[k] = 16'bxxxx_xxxx_xxxx_xxxx;
    end
    $readmemh(`TEST_DATA_FILE, DataOut);
    for (m = 0; m < 1023; m = m + 1)
    begin
      if (DataOut[m] === 16'bxxxx_xxxx_xxxx_xxxx)
      begin
        if (FileLength == 0)
        begin
          FileLength = m - 1'b1;
        end
      end
    end
  end
  else if (`DATA_TYPE == 2'b00)
  begin
    for (k = 0; k <= 255; k = k + 1)
    begin
      DataOut[k] = 0;
    end
  end
end

/*****************************************************************************
* Reset
* Sends zero's on RDat and one on RCtl.  Called when the core is in reset
*****************************************************************************/
task reset;
  begin
  RDat <= 'd0;
  RCtl <= 1'b1;
  FFWriteEn <= 1'b0;
  GetStatusChan <= 'b0;
  Stat <= 'b0;
  Chan <= 'b0;
  @(posedge RDClk2x);
end
endtask

/*****************************************************************************
* Send Packet
* Sends an entire packet NumBytes long.  It sends an SOP at the beginning
* and an EOP at the end
******************************************************************************
* Inputs
* Address: The channel to send the packet on
* NumBytes: The number of bytes to send
*****************************************************************************/
task send_packet;
input  [7:0] Address;
input  [7:0] NumBytes;
reg    [7:0] Cnt;
reg    [7:0] BytesDiv2;

begin

  //If the channel the user has selected is satisfied and CHECK_RSTAT is
  //enabled then don't send to the channel and print a warning
  if ( ((FullVec[Address] == 1) && (CheckRStat == 1)) || (SnkAlmostFull_n == 0) )  // 
  begin
   // $display("%s: Channel %d is almost full at time %0d ps", "Information", Address, $time);
    @(posedge RDClk2x);
  end

  //Otherwise send the packet
  else
  begin
    //Send an SOP payload control word to Address
    send_control({1'b0,TCDIP4Request,4'b1001, Address, 4'b1111});

    //Calculate the number of cycles the task needs to send data for.  
    if ((NumBytes % 2) == 1)
      BytesDiv2 = (NumBytes / 2) + 1;
    else
      BytesDiv2 = (NumBytes / 2);

    //Send the data
    send_words(BytesDiv2, Address);

    //Send the EOP with the mod set if the number of bytes is odd.  Otherwise
    //send it without the mod set
    if ((NumBytes % 2) == 0)
      send_control({1'b0,TCDIP4Request,16'b0100_0000_0000_1111});
    else if ((NumBytes % 2) == 1)
      send_control({1'b0, TCDIP4Request,16'b0110_0000_0000_1111});
    else
      $display ("%s: %0d Error in send packet", "ERROR", $time);

    //FIFO write enable is deasserted after all data has been written
    FFWriteEn <= 1'b0;
  end
end
endtask

/*****************************************************************************
* Send User Data
* Sends NumBytes number of bytes to Address.  The user specifies the SOP,
* EOP, and MOD for the burst.  Note: if the EOP or Err is not set it is
* possible to get an error if the burst does not stop on a credit boundary
******************************************************************************
* Inputs
* Sop: Indicates the following data is the start of a packet
* Eop: Is sent after the data indicating that it is the end of a packet
* Err: Is sent after the data indicating an EOP abort
* Address: The channel to send the data to
* NumBytes: The number of bytes of data to send
*****************************************************************************/
task send_user_data;
input       Sop;
input       Eop;
input       Err;
input [7:0] Address;
input [7:0] NumBytes;
reg   [7:0] Cnt;
reg   [7:0] BytesDiv2;
reg   [1:0] Eops;

//If the channel the user has selected is satisfied and CHECK_RSTAT is
//enabled then don't send to the channel and print a warning
if ( ((FullVec[Address] == 1) && (CheckRStat == 1)) || (SnkAlmostFull_n == 0) )  // 
begin
  // $display("%s: Channel %d is almost full at time %0d ps", "Information", Address, $time);
  @(posedge RDClk2x);
end

//Otherwise send the packet
else
begin
  //Send payload control word with Sop and Address
  send_control({1'b0, TCDIP4Request,3'b100, Sop, Address, 4'b1111});

  //Calculate the number of cycles the task needs to send data for
  if ((NumBytes % 2) == 1)
    BytesDiv2 = (NumBytes / 2) + 1;
  else
    BytesDiv2 = (NumBytes / 2);

  //Send the data
  send_words(BytesDiv2, Address);
  
  //Get the value for the control bits [14:13]
  //If err is set then it is 01
  if (Err == 1'b1)
    Eops = 2'b01;
  //If Eop is set then the mod has to be calculated
  else if (Eop == 1'b1)
  begin
    if ((NumBytes % 2) == 0)
      Eops = 2'b10;
    else if ((NumBytes % 2) == 1)
      Eops = 2'b11;
  end
  //Otherwise it is 00
  else
    Eops = 2'b00;

  //If EOPS is not '00' then send out EOP control word
  if (Eops != 2'b00)
    send_control({1'b0,TCDIP4Request,1'b0, Eops, 1'b0, 12'h00f});

  //FIFO write enable is deasserted after all data has been written
  FFWriteEn <= 1'b0;
end
endtask
  
/*****************************************************************************
* Send erred control data
* This task sends two control words in a row followed by data followed by
* another control word.
******************************************************************************
* Inputs
* Pc1: The Payload bit for the first control word (bit[15])
* Sop1: The SOP bit for the first control word
* Address1: The channel for the first control word
* Pc2: The Payload but for the second control word
* Sop2: The SOP bit for the second control word
* Address2: The channel for the second control word
* NumBytes2: The number of bytes to send after the second control word
* Eop2: Whether to set the EOP for the control word following the data
* Err2: Whether to set the Err for the control word following the data
*****************************************************************************/
task err_ctl_data;
input       Pc1;
input       Sop1;
input [7:0] Address1;
input       Pc2;
input       Sop2;
input [7:0] Address2;
input [7:0] NumBytes2;
input       Eop2;
input       Err2;
reg   [7:0] BytesDiv2;
reg   [7:0] Cnt;
reg   [1:0] Eops;

begin
  SopErr = 1'b1;

  //Send the first two control words
  send_control({1'b0,TCDIP4Request,Pc1, 2'b00, Sop1, Address1, 4'b1111});
  send_control({1'b0,TCDIP4Request,Pc2, 2'b00, Sop2, Address2, 4'b1111});

  //Calculate the number of cycles the task needs to send data for
  if ((NumBytes2 % 2) == 1)
    BytesDiv2 = (NumBytes2 / 2) + 1;
  else
    BytesDiv2 = (NumBytes2 / 2);

  //Send the data
  send_words(BytesDiv2, Address1);

  //Calculate the bits [14:13] for the last control word
  //If the Err2 signal is 1 then the bits are 01
  if (Err2 == 1'b1)
    Eops = 2'b01;
  //If the Eop2 signal is 1 then check the mod
  else if (Eop2 == 1'b1)
  begin
    if ((NumBytes2 % 2) == 0)
      Eops = 2'b10;
    else if ((NumBytes2 % 2) == 1)
      Eops = 2'b11;
  end
  //Otherwise the bits get set to zero
  else
    Eops = 2'b00;

  send_control({1'b0,TCDIP4Request,1'b0, Eops, 1'b0, 12'h00f});
  @(posedge RDClk2x);

  //FIFO write enable is deasserted after all data has been written
  FFWriteEn <= 1'b0;
  SopErr = 1'b0;
end
endtask
  
/*****************************************************************************
* Send two EOP's
* This task sends a control word, then data, then two EOP's in a row.  The
* first EOP's mod is set by the number of bytes that have been sent.  The
* second EOP's mod is set by the user
******************************************************************************
* Inputs
* Pc1: The payload bit for the first control word
* Sop1: The SOP bit for the first control word
* Address1: The channel number for the first control word
* NumBytes1: The number of data bytes to send
* Mod2: The mod value for the last control word.
*****************************************************************************/
task eop_eop;
input       Pc1;
input       Sop1;
input [7:0] Address1;
input [7:0] NumBytes1;
input       Mod2;
reg   [7:0] BytesDiv2;
reg   [7:0] Cnt;
reg   [1:0] Eops;

begin
  //Send the first control word
  send_control({1'b0,TCDIP4Request,Pc1, 2'b00, Sop1, Address1, 4'b1111});

  //Calculate the number of cycles the task needs to send data and set bits
  //[14:13] for the second control word (the first EOP)
  if ((NumBytes1 % 2) == 1)
    begin
    BytesDiv2 = (NumBytes1 / 2) + 1;
    Eops = 2'b11;
    end
  else
    begin
    BytesDiv2 = (NumBytes1 / 2);
    Eops = 2'b10;
    end

  //Send the data
  send_words(BytesDiv2, Address1);

  //Send both EOP control words
  send_control({1'b0,TCDIP4Request,1'b0, Eops, 1'b0, 12'h00f});
  send_control({1'b0,TCDIP4Request,2'b01, Mod2, 1'b0, 12'h00f});

  //FIFO write enable is deasserted after all data has been written
  FFWriteEn <= 1'b0;