pl4_lite_testcase_pkg.v

spi接口的vhdl实现

/*****************************************************************************
* SPI-4.2 Testcase Package
******************************************************************************
*
*  Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
*  This text/file contains proprietary, confidential
*  information of Xilinx, Inc., is distributed under
*  license from Xilinx, Inc., and may be used, copied
*  and/or disclosed only pursuant to the terms of a valid
*  license agreement with Xilinx, Inc. Xilinx hereby
*  grants you a license to use this text/file solely for
*  design, simulation, implementation and creation of
*  design files limited to Xilinx devices or technologies.
*  Use with non-Xilinx devices or technologies is expressly
*  prohibited and immediately terminates your license unless
*  covered by a separate agreement.
*
*  Xilinx is providing this design, code, or information
*  "as-is" solely for use in developing programs and
*  solutions for Xilinx devices, with no obligation on the
*  part of Xilinx to provide support. By providing this design,
*  code, or information as one possible implementation of
*  this feature, application or standard, Xilinx is making no
*  representation that this implementation is free from any
*  claims of infringement. You are responsible for obtaining
*  any rights you may require for your implementation.
*  Xilinx expressly disclaims any warranty whatsoever with
*  respect to the adequacy of the implementation, including
*  but not limited to any warranties or representations that this
*  implementation is free from claims of infringement, implied
*  warranties of merchantability or fitness for a particular
*  purpose.
*
*  Xilinx products are not intended for use in life support
*  appliances, devices, or systems. Use in such applications is
*  expressly prohibited.
*
*  Any modifications that are made to the Source Code are
*  done at the user's sole risk and will be unsupported.
*  The Xilinx Support Hotline does not have access to source
*  code and therefore cannot answer specific questions related
*  to source HDL.
*
*  This copyright and support notice must be retained as part
*  of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc.
*  All rights reserved.
*
******************************************************************************
* Filename: pl4_lite_testcase_pkg.v
*
* Description: This module includes constants used by the testbench.
*
******************************************************************************
* Structure: pl4_lite_testcase_pkg.v
*
*
*****************************************************************************/
`timescale 1ps/1ps

/*****************************************************************************
* Library Declarations
*****************************************************************************/

/*****************************************************************************
* Constant Declarations
*****************************************************************************/

// Testbench Parameters
`define TDCLK_PERIOD    11100`define RDCLK_PERIOD    11100`define USERCLK_PERIOD  11100
`define TFF 	            500
`define TRAINING_CTL   16'h0FFF
`define SNK_CAL_DATA    "../snk_calendar.dat"
`define SRC_CAL_DATA    "../src_calendar.dat"

// Stimulus & Testcase Module Parameters
`define NUM_CHANNELS    16
`define SNK_ALPHA_DATA 3
`define SNK_DATA_MAX_T 4000
`define MERGE_PAYLOAD  0
`define CHECK_RSTAT    1'b0
`define DATA_TYPE      2'b00
`define TEST_DATA_FILE "../data_file.dat"
`define RANDOM_SEED    5431
`define DATA_NUM_TRAIN_SEQ 4'd3

// Default values for Sink Static Configuration Parameters
`define SnkCalendar_M_default       0
`define SnkCalendar_Len_default     15
`define FifoAFMode_default          1

// Default values for Source Static Configuration Parameters
`define SrcBurstLen_default         32
`define SrcBurstMode_default        1
`define SrcCalendar_M_default       0
`define SrcCalendar_Len_default     15
`define DataMaxT_default            4096
`define AlphaData_default           2