pl4_lite_stimulus.v

spi接口的vhdl实现

/*****************************************************************************
* SPI-4.2 Stimulus Module
******************************************************************************
*
*  Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
*  This text/file contains proprietary, confidential
*  information of Xilinx, Inc., is distributed under
*  license from Xilinx, Inc., and may be used, copied
*  and/or disclosed only pursuant to the terms of a valid
*  license agreement with Xilinx, Inc. Xilinx hereby
*  grants you a license to use this text/file solely for
*  design, simulation, implementation and creation of
*  design files limited to Xilinx devices or technologies.
*  Use with non-Xilinx devices or technologies is expressly
*  prohibited and immediately terminates your license unless
*  covered by a separate agreement.
*
*  Xilinx is providing this design, code, or information
*  "as-is" solely for use in developing programs and
*  solutions for Xilinx devices, with no obligation on the
*  part of Xilinx to provide support. By providing this design,
*  code, or information as one possible implementation of
*  this feature, application or standard, Xilinx is making no
*  representation that this implementation is free from any
*  claims of infringement. You are responsible for obtaining
*  any rights you may require for your implementation.
*  Xilinx expressly disclaims any warranty whatsoever with
*  respect to the adequacy of the implementation, including
*  but not limited to any warranties or representations that this
*  implementation is free from claims of infringement, implied
*  warranties of merchantability or fitness for a particular
*  purpose.
*
*  Xilinx products are not intended for use in life support
*  appliances, devices, or systems. Use in such applications is
*  expressly prohibited.
*
*  Any modifications that are made to the Source Code are
*  done at the user's sole risk and will be unsupported.
*  The Xilinx Support Hotline does not have access to source
*  code and therefore cannot answer specific questions related
*  to source HDL.
*
*  This copyright and support notice must be retained as part
*  of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc.
*  All rights reserved.
*
******************************************************************************
* Filename: pl4_lite_stimulus.v
*
* Description: The stimulus module either transmits data from the testcase
* module to the core, or stores that data and send its own data to the core.
* This data may be training and framing data between the testbench and the
* core or other data.  The strimulus module also calculates the DIP4 and DIP2 
* checksums and transmits them to the core
*
****************************************************************************/

`timescale 1ps/1ps

/****************************************************************************
* Library Declaration
****************************************************************************/
`include "../pl4_lite_testcase_pkg.v"

/****************************************************************************
* Module Declarations
****************************************************************************/
module pl4_lite_stimulus (
  //System Signals
  Reset_n,
  RDClk2x,
  SysClk,
  TSClkIn,
  UserClk,

  //Testcase signals
  TCStat,
  TCChannel,
  TCCtl,
  TCDat,
  TCIdleRequest,
  TCTrainingRequest,
  TCSnkDip2ErrRequest,
  CtlFull,
  FFWriteEn,
  SopErr,
  GetStatusChan,
  GetStatus,
  TCDIP2Request,

  //Sink Interface
  RDClk_P,
  RDClk_N,
  RDat_P,
  RDat_N,
  RCtl_P,
  RCtl_N,
  
  //Source Interface
  SrcCalendar_M,
  SrcCalendar_Len,
  IdleRequest,
  TrainingRequest,
  SnkDip2ErrRequest,

  TStat,
  TSClk,

  //Calendar Loading Signals
  CalWrEn_n,
  CalAddr,
  CalData,

  //Monitor Signals
  SnkAlmostFull_n ,  // rle
  SnkInFrame,
  SrcInFrame
);


/*********************************************************************
* Parameter Declarations
*********************************************************************/
parameter        SnkAlphaData  = 'd3;
parameter        SnkDataMaxT   = 'd4000;
parameter        MergePayload  = 'd0;
parameter        NumLinks      = 'd16;
parameter        CheckRStat  = 'd0;
parameter        DataType    = 'b01;
parameter        RandomSeed  = 'd5431;

//System Signals
input         Reset_n;
input         RDClk2x;
input         SysClk;
input         TSClkIn;
input         UserClk;

//Testcase signals
input  [1:0]  TCStat;
input  [15:0] TCChannel;
input         TCCtl;
input  [17:0] TCDat;
input         TCIdleRequest;
input         TCTrainingRequest;
input         TCSnkDip2ErrRequest;
output        CtlFull;
input         FFWriteEn;
input         SopErr;
input  [7:0]  GetStatusChan;
output [1:0]  GetStatus;
input         TCDIP2Request;

//Sink Interface
output        RDClk_P;
output        RDClk_N;
output [15:0] RDat_P;
output [15:0] RDat_N;
output        RCtl_P;
output        RCtl_N;
 
//Source Interface
input  [7:0]  SrcCalendar_M;
input  [8:0]  SrcCalendar_Len;
output        IdleRequest;
output        TrainingRequest;
output        SnkDip2ErrRequest;
output  [1:0] TStat;
output        TSClk;

// Calender Loader Signals
input         CalWrEn_n;
input  [8:0]  CalAddr;
input  [7:0]  CalData;

//Monitor Signals
input         SnkInFrame;
input         SrcInFrame;
input         SnkAlmostFull_n ; // rle

wire          SnkAlmostFull_n ; // rle
wire          Reset_n;
wire          RDClk2x;
wire          SysClk;
wire          TSClkIn;
wire          UserClk;
wire   [1:0]  TCStat;
wire  [15:0] TCChannel;
wire          TCCtl;
wire   [17:0] TCDat;
wire          TCIdleRequest;
wire          TCTrainingRequest;
wire          TCSnkDip2ErrRequest;
wire          CtlFull;
wire          FFWriteEn;
wire          SopErr;
wire   [7:0]  GetStatusChan;
reg    [1:0]  GetStatus;
wire          TCDIP2Request;
reg           RDClk_P;
reg           RDClk_N;
wire   [15:0] RDat_P;
wire   [15:0] RDat_N;
wire          RCtl_P;
wire          RCtl_N;
wire          IdleRequest;
wire          TrainingRequest;
wire          SnkDip2ErrRequest;
reg    [1:0]  TStat;
wire          TSClk;
wire          CalWrEn_n;
wire   [8:0]  CalAddr;
wire   [7:0]  CalData;
wire          SnkInFrame;
wire          SrcInFrame;
integer       i;

 
/******************************************************************************
* Definition of Parameters:
*   SnkAlphaData           :  Number of repetitions of the training pattern
*                             sent to the Sink Core
*   SnkDataMaxT            :  Number of cycles between training patterns sent
*                             to the Sink Core
*   MergePayload           :  Whether to allow merging of back-to-back Payload
*                             Control & EOP words
*   NumLinks               :  Number of channels
*   CheckRStat             :  Whether to check fullness of channel before
*                             beginning to send a packet
*   DataType               :  Whether to send incrementing, random, or file
*                             data
*   RandomSeed             :  Seed for random number generator
*******************************************************************************
* Definition of Ports:
*******************************************************************************
* System Signals
*   Reset_n                :  Input Reset (active low)
*   RDClk2x                :  clock used for the creation of data to be sent
*                             to the core (default 800Mhz)
*   SysClk                 :  System Clock (default 400Mhz)
*   TSClkIn                :  Input clock from the clock generator used to
*                             create the status signal
*   UserClk                :  Clock used for calendar programming
* Testcase Signals
*   TCStat                 :  Status signal from the testcase module
*   TCChannel              :  The channel number to write TCStat
*   TCCtl                  :  Control Signal from the testcase module
*   TCDat                  :  Data bus from the testcase module
*   TCIdleRequest          :  Signal from the testcase module indicating the
*                             control module should send an idle request to 
*                             the core
*   TCTrainingRequest      :  Signal from the testcase mdoule indicating the
*                             control module should send a training request to
*                             the core
*   TCSnkDip2ErrRequest    :  Signal from the testcase mdoule indicating the
*                             Sink Core should send invalid DIP2
*                             calculations.
*   CtlFull                :  Signal from the control module to the testcase
*                             module indicating that its buffers are full
*                             and the testcase module should stop sending data
*   FFWriteEn              :  Indicates that there is valid data on TCDat
*                             and TCCtl
*   SOPErr                 :  Indicates that there is a user specified SOP
*                             spacing error on the data being sent from the
*                             testcase module.  The control module
*                             therefore should not force minimum SOP
*                             spacing for the packet.
*   GetStatusChan          :  Signal indicating which channel it should
*                             send status for
*   GetStatus              :  Contains the status of the channel specified
*                             by GetStatusChan.  This is sent to the
*                             Testcase module
*   TCDIP2Request          :  Indicates that DIP2 errors should be sent on
*                             TStat while this signal is active.
* Sink Interface
*   RDClk                  :  Source synchronous clock received with RDat
*   RDat                   :  The 16-bit SPI-4.2 data bus
*   RCtl                   :  SPI-4.2 interface signal that defines whether 
*                             data or control information is present on the 
*                             RDat bus
* Source Interface
*   IdleRequest            :  Signal that requests idle control words be sent 
*                             out on the Source interface
*   TrainingRequest        :  Signal that requests training patterns be sent 
*                             on the Source interface
*   SnkDip2ErrRequest      :  Signal that requests invalid DIP2 calculations
*                             be sent from the Sink Core. 
*   TStat                  :  Source status signal
*   TSClk                  :  Source synchronous clock transmitted with TStat
* Calendar Signals
*   CalWrEn_n              :  Signal to enable writing of the calendar
*   CalAddr                :  The bus containing the address to write the
*                             calendar number indicated on the CalData bus
*                             when CalWrEn_n is asserted
*   CalData                :  The bus containing the channel number to
*                             write into the calendar buffer
* Monitor Signals
*   SnkInFrame             :  Signal from the monitor block that indicates that
*                             the Sink core is in frame
*   SrcInFrame             :  Signal from the monitor block that indicates that 
*                             the Source core is in frame
*********************************************************************/

/*********************************************************************
* Signal Declarations
*********************************************************************/
reg  [15:0] TrainingCnt;         //number of cycles since last training
reg  [7:0]  CalSeq [511:0];      //Calendar buffer containing channel number
//Fifo signals to capture incoming data from the testcase module
reg  [9:0]  TCDatFFBottom;       //Current index to read from
reg  [9:0]  TCDatFFTop;          //Current index to write to
reg  [18:0] TCDatFF [1023:0];    //Buffer for incoming data (TCDat)
                                 //Bit 18 is for Sop Spacing Error signal
                                 //Bit 17 is reserved for future use
                                 //Bit 16 is for DIP4 error insertion
reg         TCCtlFF [1023:0];    //Buffer for TCCtl signal
reg         FirstRead;           //Used to delay writing to the fifo one cycle
reg         CtlEmpty;            //Indicates that the data FIFO is empty
reg         AlmostFull;          //Indicates the data FIFO has one empty slot
reg         AlmostEmpty;         //Indicates the data FIFO has one full slot
reg         CtlFull_i;           //Internal version of CtlFull output
//Signals for sending data to the Core
reg  [7:0]  CurrentAddress;      //Current address that data is being sent to
reg  [15:0] DataInterrupt;       //Data to be sent after an idle burst
reg  [9:0]  x;                   //Counter
reg         HasEOP;
reg         HasCredit;
wire [17:0] RDat;                //Data bus before DIP4 calculation
wire        RCtl;                //Control signal before DIP4 calculation
reg  [2:0]  SopCnt;              //number of cycles since last SOP
reg  [2:0]  CreditCnt;           //number of cycles since last credit
reg         CreditBoundary;      //Signal indicating on a credit boundary