pl4_lite_data_monitor.v

spi接口的vhdl实现

/*****************************************************************************
* SPI-4.2 Data Monitor
******************************************************************************
*
*  Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
*  This text/file contains proprietary, confidential
*  information of Xilinx, Inc., is distributed under
*  license from Xilinx, Inc., and may be used, copied
*  and/or disclosed only pursuant to the terms of a valid
*  license agreement with Xilinx, Inc. Xilinx hereby
*  grants you a license to use this text/file solely for
*  design, simulation, implementation and creation of
*  design files limited to Xilinx devices or technologies.
*  Use with non-Xilinx devices or technologies is expressly
*  prohibited and immediately terminates your license unless
*  covered by a separate agreement.
*
*  Xilinx is providing this design, code, or information
*  "as-is" solely for use in developing programs and
*  solutions for Xilinx devices, with no obligation on the
*  part of Xilinx to provide support. By providing this design,
*  code, or information as one possible implementation of
*  this feature, application or standard, Xilinx is making no
*  representation that this implementation is free from any
*  claims of infringement. You are responsible for obtaining
*  any rights you may require for your implementation.
*  Xilinx expressly disclaims any warranty whatsoever with
*  respect to the adequacy of the implementation, including
*  but not limited to any warranties or representations that this
*  implementation is free from claims of infringement, implied
*  warranties of merchantability or fitness for a particular
*  purpose.
*
*  Xilinx products are not intended for use in life support
*  appliances, devices, or systems. Use in such applications is
*  expressly prohibited.
*
*  Any modifications that are made to the Source Code are
*  done at the user's sole risk and will be unsupported.
*  The Xilinx Support Hotline does not have access to source
*  code and therefore cannot answer specific questions related
*  to source HDL.
*
*  This copyright and support notice must be retained as part
*  of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc.
*  All rights reserved.
*
******************************************************************************
* Filename: pl4_lite_data_monitor.v
*
* Description: Monitors the data sent from the Demonstration Testbench to
* the Core and the data sent from the Core to the testbench to ensure that
* they are the same (minus any idles or training).  It also informs
* the Control module when to send framing via the SrcInFrame signal.
*
****************************************************************************/

`timescale 1ps/1ps

`include "../pl4_lite_testcase_pkg.v"

/****************************************************************************
* Module Declarations
****************************************************************************/
module pl4_lite_data_monitor(
  // System Signals
  Reset_n,

  // Sink Core Signals
  RCtl,
  RDat,
  RDClk,

  // Source Core Signals
  TCtl,
  TDat,
  TDClk,
  IdleRequest,
  TrainingRequest,
  DataMaxT,
  AlphaData,
  NumTrainSequences,
  SrcBurstLen,
  SrcBurstMode,
  SrcOof,
  SrcEn,
  SnkOof,
  SnkFFEmpty_n,  
  SnkEn,
  TCComplete,

  // Control Module Signals
  SrcInFrame
);

input        Reset_n;
input        RCtl;
input [15:0] RDat;
input        RDClk;
input        TCtl;
input [15:0] TDat;
input        TDClk;
input        IdleRequest;
input        TrainingRequest;
input [15:0] DataMaxT;
input [7:0]  AlphaData;
input [3:0]  NumTrainSequences;
input [5:0]  SrcBurstLen;
input        SrcBurstMode;
input        SrcOof;
input        SrcEn;
input        SnkOof;
input        SnkFFEmpty_n;
input        SnkEn;
input 	     TCComplete;
output       SrcInFrame;

wire         Reset_n;
wire         RCtl;
wire  [15:0] RDat;
wire         RDClk;
wire         TCtl;
wire  [15:0] TDat;
wire         TDClk;
wire         IdleRequest;
wire         TrainingRequest;
wire  [15:0] DataMaxT;
wire  [7:0]  AlphaData;
wire  [5:0]  SrcBurstLen;
wire         SrcBurstMode;
wire         SrcOof;
wire         SrcEn;
reg          SrcInFrame;

/*****************************************************************************
* Definition of Ports
******************************************************************************
* System Signals
*   Reset_n                :  Input Reset (active low)
* Sink Core Signals
*   RCtl                   :  SPI-4.2 interface signal that defines whether
*                             data or control information is present on the
*                             RDat bus
*   RDat                   :  The 16-bit SPI-4.2 data bus from the Sink
*                             Core
*   RDClk                  :  Source synchronous clock received with RDat
* Source Core Signals
*   TCtl                   :  SPI-4.2 interface signal that defines whether
*                             data or control information is present on the
*                             TDat bus
*   TDat                   :  The 16-bit SPI-4.2 data bus from the Source
*                             Core
*   TDClk                  :  Source synchronous clock received with TDat
*   IdleRequest            :  Signal that requests idle control words be sent
*                             out on the Source interface
*   TrainingRequest        :  Signal that requests training patterns be sent
*                             on the Source interface
*   DataMaxT               :  Maximum interval between scheduling of training
*                             cycles on data path
*   AlphaData              :  Number of repititions of the training pattern
*   NumTrainSequences      :  Number of training sequences to receive before
*                             asserting SrcInFrame
*   SrcBurstLen            :  Maximum length of packet (in credits) the
*                             core will send before splitting the data into
*                             multiple packets.
*   SrcBurstMode           :  If equal to 0 source will send once a credit
*                             of data is writtern into the fifo.  If 1 the
*                             source will wait for either an EOP or
*                             SrcBurstLen number of credits before sending
*                             anything.
*   SrcOof                 :  Signal indicating that the Souce Core is not
*                             in frame.  It is set after receipt of
*                             consecutive DIP2 matches.
*   SrcEn                  :  Signal from startup block enabling the source
*                             core.
*   SrcInFrame             :  Signal indicating that the Control module can
*                             begin sending valid status.  It is set after
*                             receipt of NumTrainSequences number of
*                             training patterns.
*****************************************************************************/

/*****************************************************************************
* Constant Declarations
*****************************************************************************/
`define STORAGE_SIZE        (4096*2)  // Size of RDat and RCtl buffers
`define LOG2_STORAGE_SIZE   13        // Log base 2 of STORAGE_SIZE

/*****************************************************************************
* Signal Declarations
*****************************************************************************/
// Signals for RDat interpretation
reg  [15:0] RDatData [`STORAGE_SIZE - 1:0];     // Buffer to store RDat into
reg         RCtlData [`STORAGE_SIZE - 1:0];     // Buffer to store RCtl into
reg  [`LOG2_STORAGE_SIZE - 1:0] RDatDataIndex;  // Write pointer into RDatData
                                               // and RCtlData
reg         FirstPC;             // Flag set when first valid payload control
                                 // word is received on RDat.
reg  [7:0]  RDatTrainPatterns;   // Number of training patterns sent on RDat
reg         SrcOofPulse;         // Indicates a rising edge on SrcOof
reg         SrcOofLast;          // Stores the last value of SrcOof
reg         InTraining;          // Indicates training on RDat
reg  [2:0]  CreditCnt;           // Counts the number of cycles since last
                                 // credit boundary
reg  [5:0]  BurstCnt;            // Counts the number of credits between
                                 // payload control words on RDat
reg  [2:0]  SopCnt;              // Number of cycles since last SOP on RDat
reg         CreditBoundary;      // High when RDat is on a credit boundary
reg         CreditBoundaryLast;  // The last value of CreditBoundary
reg  [7:0]  CurrentAddress;      // Stores the address RDat is currently
                                 // sending on
reg  [15:0] TrainingCnt;         // Counts number of training sequences that
                                 // have been sent on RDat (This is used to
                                 // ensure a complete training pattern is sent)
reg [31:0]  cnt;                 // Generic counting variable

wire [`LOG2_STORAGE_SIZE - 1:0] RDatDataIndexPlus1;
                              // Equal to (RDatDataIndex + 1) mod STORAGE_SIZE
wire [`LOG2_STORAGE_SIZE - 1:0] RDatDataIndexPlus2;
                              // Equal to (RDatDataIndex + 2) mod STORAGE_SIZE
wire [`LOG2_STORAGE_SIZE - 1:0] RDatDataIndexMinus1;
                              // Equal to (RDatDataIndex - 1) mod STORAGE_SIZE
wire [`LOG2_STORAGE_SIZE - 1:0] RDatDataIndexMinus2;
                              // Equal to (RDatDataIndex - 2) mod STORAGE_SIZE


// Signals for TDat interpretation
reg  [`LOG2_STORAGE_SIZE - 1:0] TDatDataIndex;  // Index to compare the RDatData
                                               // and RCtlData arrays to
                                               // TDat and TCtl
reg  [7:0]  TDatTrainPatterns;   // Number of training patterns sent on TDat
reg         TDatTraining;        // Indicates training on TDat
reg         SrcOofTrain;         // Indicates that the Source Core was out of
                                 // frame when training was sent
reg  [2:0]  TDatSopCnt;          // Number of cycles since last SOP on TDat
reg  [15:0] TDatTrainingCnt;     // Counts number of training sequences that
                                 // have been sent on TDat (This is used to
                                 // ensure a complete training pattern is sent)
reg  [6:0]  SinceIdleRequest;
reg         TDatFirst;           // Indicates first data has been sent on TDat
reg  [15:0] TDatSinceTrain;      // Number of cycles since last training was
                                 // sent on TDat
reg         TrainingRequestLast; // Stores the last value of training request
reg         TrainingRequestSent; // Asserted once TrainingRequest is pulsed
                                 // until training begins
reg  [6:0]  SinceTrainReq;       // Number of cycles since TrainingRequest was
                                 // asserted
reg  [4:0]  AlphaDataCnt;        // Counts the number of Training words sent
                                 // on TDat
reg  [7:0]  AlphaDataPatternCnt; // Counts the number of Training Patterns sent
                                 // on TDat
reg         FirstTrain;          // Indicates source core is enabled and sent
                                 // first training pattern on TDat.
reg         PCFlag;              // Checks for payload control word after a
                                 // training request signal has been
                                 // received
reg         FirstIdle;           // Idicates one idle has been received before
                                 // training data is sent in response to
                                 // TrainingRequest.
reg         TrainReqPulse;       // Asserted at the leading edge of
                                 // TrainingRequest
reg         TDatResetComplete;   // Asserted once TDat/TCtl OSERDES should have
                                 // completed the reset process
reg  [4:0]  ClkCnt;              // Counter used in tdat_reset_delay

// Signals For DIP4 Calculation
reg         TCtl_s;              // Registered TCtl signal
reg  [15:0] TDat_s;              // Registered TDat signal
reg         TCtl_d1;             // One clock cycle delay of TCtl_s
reg  [15:0] TDat_d1;             // One clock cycle delay of TDat_s
reg  [15:0] DIP16;               // Registered Dip16 calculation
reg  [15:0] NextDIP16;           // Combinatorial Dip16 calculation
reg  [3:0]  DIP4;                // Registered Dip4 Calculation
wire [3:0]  NextDIP4;            // Combinatorial Dip4 Calculation
reg         Training;            // Indicates in training during DIP4 calc
reg         BufferOverflow;      // Indicates Overflow in Monitor Buffer
reg         BufferEmpty;         // Indicates Empty in Monitor Buffer

wire       TDClk_align;          //TDClk aligned to TDat data eye

 // Signals For Core Flags 
reg 	     BothEnabled_d1; 
reg 	     BothEnabled_d2;
reg          ValidCheck;
reg 	     BothInFrame_d1;
reg 	     BothInFrame_d2;
reg 	     SnkOof_d1;
reg 	     SnkOof_d2;
reg 	     SrcOof_d1;
reg 	     SrcOof_d2;
reg 	     GotFirstTDat;
reg 	     SnkFFEmpty_n_d1;
reg 	     SnkFFEmpty_n_d2;
reg 	     RDatFirst;

/*****************************************************************************
* Signal Initialization
*****************************************************************************/
initial
  begin
     SrcOofLast        = 1'b1;
     SrcOofTrain       = 1'b0;
     FirstIdle         = 1'b0;
     TrainReqPulse     = 1'b0;
     TDatResetComplete = 1'b0;
  end

assign  RDatDataIndexPlus1   = (RDatDataIndex + 'd1) % `STORAGE_SIZE;
assign  RDatDataIndexPlus2   = (RDatDataIndex + 'd2) % `STORAGE_SIZE;
assign  RDatDataIndexMinus1  = (RDatDataIndex - 'd1) % `STORAGE_SIZE;
assign  RDatDataIndexMinus2  = (RDatDataIndex - 'd2) % `STORAGE_SIZE;



//****************************************************************************
// Emulate Static Alignment: Delay the TDClk to align it to the TDat data eye
//****************************************************************************
assign  #(`TDCLK_PERIOD/4) TDClk_align = TDClk  ; // rle

//****************************************************************************
// Interpret RDat
//****************************************************************************
// Reads the data and control words off of the RDat bus and stores them into
// ReceievedData.  It ignores idle and training words and also removes
// errored data according to the spec.  It processes the following:
// 1. Drops all data until first valid SOP payload control word is received
// 2. Changes reserved control words to PC when followed by data