uart232_pl4_lite_snk_top.veo

spi接口的vhdl实现

/*******************************************************************
* This file is owned and controlled by Xilinx and must be used     *
* solely for design, simulation, implementation and creation of    *
* design files limited to Xilinx devices or technologies. Use      *
* with non-Xilinx devices or technologies is expressly prohibited  *
* and immediately terminates your license.                         *
*                                                                  *
* Xilinx products are not intended for use in life support         *
* appliances, devices, or systems. Use in such applications are    *
* expressly prohibited.                                            *
*                                                                  *
* Copyright (C) 2001, Xilinx, Inc.  All Rights Reserved.           *
*******************************************************************/

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

uart232_pl4_lite_snk_top YourInstanceName (
    // common signals
    .reset_n            (Reset_n),
    .snkfiforeset_n     (SnkFifoReset_n),

    .dcmlost_rdclk      (DcmLost_RDClk),
    .dcmreset_rdclk     (DcmReset_RDClk),
    .locked_rdclk       (Locked_RDClk),
    .snkclksrdy         (SnkClksRdy),

    // sink general purpose clocks
    .rdclk180_gp        (RDClk180_GP),
    .rdclk0_gp          (RDClk0_GP),


    // Sink Calendar I/O
    .snkcalendar_m      (SnkCalendar_M),
    .snkcalendar_len    (SnkCalendar_Len),
    .snkcalclk          (SnkCalClk),
    .snkcalwren_n       (SnkCalWrEn_n),
    .snkcaladdr         (SnkCalAddr),
    .snkcaldata         (SnkCalData),
    .snkcaldataout      (SnkCalDataOut),
    .snkstatclk         (SnkStatClk),
    .snkstat            (SnkStat),
    .snkstataddr        (SnkStatAddr),
    .snkstatwr_n        (SnkStatWr_n),
    .snkstatmask        (SnkStatMask),

    // FIFO I/O
    .snkffclk           (SnkFFClk),
    .snkffrden_n        (SnkFFRdEn_n),
    .snkffaddr          (SnkFFAddr),
    .snkffdata          (SnkFFData),
    .snkffmod           (SnkFFMod),
    .snkffsop           (SnkFFSOP),
    .snkffeop           (SnkFFEOP),
    .snkffbursterr      (SnkFFBurstErr),
    .snkfferr           (SnkFFErr),
    .snkffdip4err       (SnkFFDIP4Err),
    .snkffpayloaderr    (SnkFFPayloadErr),
    .snkffpayloaddip4   (SnkFFPayloadDIP4),

    .snkffvalid         (SnkFFValid),
    .snkffempty_n       (SnkFFEmpty_n),
    .snkffalmostempty_n (SnkFFAlmostEmpty_n),
    .snkalmostfull_n    (SnkAlmostFull_n),
    .snkoverflow_n      (SnkOverflow_n),

    // Control and status signals
    .snken              (SnkEn),
    .snkoof             (SnkOof),
    .snkbuserr          (SnkBusErr),
    .snkbuserrstat      (SnkBusErrStat),
    .snktrainvalid      (SnkTrainValid),
    .snkdip2errrequest  (SnkDIP2ErrRequest),

    // FIFO status interface
    .rsclk              (RSClk),
    .rstat              (RStat),

    // PL4 sink bus
    .rdclk_p            (RDClk_P),
    .rdclk_n            (RDClk_N),
    .rdat_p             (RDat_P),
    .rdat_n             (RDat_N),
    .rctl_p             (RCtl_P),
    .rctl_n             (RCtl_N),

    // Configuration signals
    .snkafthresassert   (SnkAFThresAssert),
    .snkafthresnegate   (SnkAFThresNegate),
    .fifoafmode         (FifoAFMode),
    .numdip4errors      (NumDip4Errors),
    .numtrainsequences  (NumTrainSequences),
    .rsclkphase         (RSClkPhase),
    .rsclkdiv           (RSClkDiv));

// INST_TAG_END ------ End INSTANTIATION Template ---------