uart232_pl4_lite_snk_top.prj

spi接口的vhdl实现

pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_pkg.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\srl_pipe.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\generic_fifo_pkg.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\rloc_package.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\dip4_calc.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_dpmsrsw_cal.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_dpmsrsw_cal_v5.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_sync_1shot_rising.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_sync_fifo_reset.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_sync_it.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\pl4_lite_sync_reset.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\running_crc.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\common\crc.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_reg_gray.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_wr.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_ram.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_ram_v5.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo_rd.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_generic_fifo.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_cal.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_reset.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_sync.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_synchronizer.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_wr_par.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_wr.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_wr64.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_afifo.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_core.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_io_ddr0.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_io_ddr1.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_io_buffer.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_io.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_clk.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_top.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\snk\pl4_lite_snk_top_user_clk.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_reset.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_synchronizer.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_reg_gray.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_ram.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_ram_v5.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_rd.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo_wr.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_async_burst_fifo.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_fifo.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_fifo_64.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_dip2.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_fifo.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_fifo_trns.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_proc.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal_trns.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_cal.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_write.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_write_64.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_data_payload.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_data_barrel.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_data_dip4.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_data.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_train_create.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_core.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_core_64.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_io_ce.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_io_ddr0.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_io_ddr1.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_io.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_clk.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_top_master_addr.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_top_master_trans.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_top_slave_addr.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\pl4_lite_v4_2\src\pl4_lite_src_top_slave_trans.vhd"
pl4_lite_v4_2 "F:\hawaii_f\ise\spi\spi_controller\tmp\_cg\_bbx\uart232_pl4_lite_snk_top.vhd"
nosort