hdllib.ref

spi接口的vhdl实现

AR pl4_lite_snk_reset xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_reset.vhd sub00/vhpl41 1217583171
EN generic_fifo_wr NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_generic_fifo_wr.vhd sub00/vhpl28 1217583158
AR pl4_lite_dpmsrsw_cal xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/pl4_lite_dpmsrsw_cal.vhd sub00/vhpl11 1217583141
AR pl4_lite_src_cal_dip2 xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_cal_dip2.vhd sub00/vhpl91 1217583221
AR pl4_lite_snk_cal xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_cal.vhd sub00/vhpl39 1217583169
EN pl4_lite_sync_reset NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/pl4_lite_sync_reset.vhd sub00/vhpl20 1217583150
AR pl4_lite_snk_io_ddr1 xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_io_ddr1.vhd sub00/vhpl59 1217583189
AR generic_fifo_rd xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_generic_fifo_rd.vhd sub00/vhpl35 1217583165
AR pl4_lite_src_cal xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_cal.vhd sub01/vhpl101 1217583231
EN pl4_async_burst_fifo NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_async_burst_fifo.vhd sub00/vhpl84 1217583214
EN pl4_async_burst_fifo_ram NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_async_burst_fifo_ram.vhd sub00/vhpl76 1217583206
EN pl4_lite_sync_1shot_rising NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/pl4_lite_sync_1shot_rising.vhd sub00/vhpl14 1217583144
AR pl4_lite_snk_wr64 xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_wr64.vhd sub00/vhpl51 1217583181
EN dip4_calc NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/dip4_calc.vhd sub00/vhpl08 1217583138
EN pl4_async_burst_fifo_ram_v5 NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_async_burst_fifo_ram_v5.vhd sub00/vhpl78 1217583208
EN pl4_lite_snk_wr64 NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_wr64.vhd sub00/vhpl50 1217583180
AR pl4_lite_src_data_dip4 xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_data_dip4.vhd sub01/vhpl111 1217583241
EN pl4_lite_snk_sync NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_sync.vhd sub00/vhpl42 1217583172
AR pl4_lite_snk_synchronizer xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_synchronizer.vhd sub00/vhpl45 1217583175
EN pl4_lite_src_cal NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_cal.vhd sub01/vhpl100 1217583230
EN pl4_lite_snk_synchronizer NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_synchronizer.vhd sub00/vhpl44 1217583174
EN pl4_async_burst_fifo_rd NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_async_burst_fifo_rd.vhd sub00/vhpl80 1217583210
AR pl4_lite_src_io_ce xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_io_ce.vhd sub01/vhpl121 1217583251
EN pl4_lite_src_top_master_addr NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_top_master_addr.vhd sub01/vhpl130 1217583260
PH rlocs NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/rloc_package.vhd sub00/vhpl06 1217583136
AR pl4_lite_src_top_master_trans xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_top_master_trans.vhd sub01/vhpl133 1217583263
EN pl4_lite_snk_io NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_io.vhd sub00/vhpl62 1217583192
AR crc rtl F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/crc.vhd sub00/vhpl25 1217583155
EN pl4_lite_src_cal_trns NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_cal_trns.vhd sub00/vhpl98 1217583228
AR generic_fifo_ram gates F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_generic_fifo_ram.vhd sub00/vhpl31 1217583161
AR pl4_lite_src_top_master_addr xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_top_master_addr.vhd sub01/vhpl131 1217583261
AR pl4_lite_src_data xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_data.vhd sub01/vhpl113 1217583243
EN pl4_lite_src_top_slave_trans NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_top_slave_trans.vhd sub01/vhpl136 1217583266
AR pl4_lite_snk_io_ddr0 xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_io_ddr0.vhd sub00/vhpl57 1217583187
AR srl_pipe xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/srl_pipe.vhd sub00/vhpl03 1217583133
AR pl4_async_burst_fifo xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_async_burst_fifo.vhd sub00/vhpl85 1217583215
EN running_crc NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/running_crc.vhd sub00/vhpl22 1217583152
EN pl4_lite_snk_cal NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_cal.vhd sub00/vhpl38 1217583168
AR pl4_lite_sync_fifo_reset xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/pl4_lite_sync_fifo_reset.vhd sub00/vhpl17 1217583147
AR pl4_async_burst_fifo_ram_v5 gates F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_async_burst_fifo_ram_v5.vhd sub00/vhpl79 1217583209
AR pl4_lite_src_io_ddr1 xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_io_ddr1.vhd sub01/vhpl125 1217583255
EN pl4_lite_src_io_ddr0 NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_io_ddr0.vhd sub01/vhpl122 1217583252
AR pl4_lite_snk_io_buffer xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_io_buffer.vhd sub00/vhpl61 1217583191
PH pl4_pkg NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/pl4_pkg.vhd sub00/vhpl00 1217583130
EN pl4_lite_src_io_ddr1 NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_io_ddr1.vhd sub01/vhpl124 1217583254
AR pl4_async_burst_fifo_wr xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_async_burst_fifo_wr.vhd sub00/vhpl83 1217583213
AR pl4_lite_src_top_slave_trans xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_top_slave_trans.vhd sub01/vhpl137 1217583267
EN pl4_lite_src_data_payload NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_data_payload.vhd sub01/vhpl106 1217583236
EN pl4_async_burst_fifo_wr NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_async_burst_fifo_wr.vhd sub00/vhpl82 1217583212
AR pl4_lite_src_cal_proc xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_cal_proc.vhd sub00/vhpl97 1217583227
EN pl4_lite_src_cal_dip2 NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_cal_dip2.vhd sub00/vhpl90 1217583220
AR dip4_calc rtl F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/dip4_calc.vhd sub00/vhpl09 1217583139
EN pl4_lite_src_data_dip4 NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_data_dip4.vhd sub01/vhpl110 1217583240
AR pl4_lite_snk_core xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_core.vhd sub00/vhpl55 1217583185
AR pl4_async_burst_fifo_rd xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_async_burst_fifo_rd.vhd sub00/vhpl81 1217583211
EN pl4_lite_snk_wr_par NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_wr_par.vhd sub00/vhpl46 1217583176
EN uart232_pl4_lite_snk_top NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/uart232_pl4_lite_snk_top.vhd sub01/vhpl138 1217583268
EN pl4_lite_src_clk NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_clk.vhd sub01/vhpl128 1217583258
EN pl4_lite_snk_reset NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_reset.vhd sub00/vhpl40 1217583170
EN pl4_lite_sync_it NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/pl4_lite_sync_it.vhd sub00/vhpl18 1217583148
AR pl4_lite_dpmsrsw_cal_v5 xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/common/pl4_lite_dpmsrsw_cal_v5.vhd sub00/vhpl13 1217583143
EN pl4_lite_src_train_create NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_train_create.vhd sub01/vhpl114 1217583244
EN pl4_lite_snk_top_user_clk NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_top_user_clk.vhd sub00/vhpl68 1217583198
EN pl4_lite_snk_io_buffer NULL F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_io_buffer.vhd sub00/vhpl60 1217583190
AR pl4_lite_src_cal_trns xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_cal_trns.vhd sub00/vhpl99 1217583229
AR pl4_lite_src_synchronizer xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_synchronizer.vhd sub00/vhpl73 1217583203
AR pl4_lite_snk_wr xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/snk/pl4_lite_snk_wr.vhd sub00/vhpl49 1217583179
AR pl4_lite_src_top_slave_addr xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_top_slave_addr.vhd sub01/vhpl135 1217583265
AR pl4_lite_src_io_ddr0 xilinx F:/hawaii_f/ise/spi/spi_controller/tmp/_cg/_bbx/pl4_lite_v4_2/src/pl4_lite_src_io_ddr0.vhd sub01/vhpl123 1217583253