xil_3624_48.in

spi接口的vhdl实现

SET_FLAG DEBUG FALSE
SET_FLAG MODE INTERACTIVE
SET_FLAG STANDALONE_MODE FALSE
SET_COMMAND_CONTEXT STRING webbrowserpath C:\Program Files\Internet Explorer\IEXPLORE.EXE
SET_COMMAND_CONTEXT STRING pdfviewerpath "D:\Program Files\Adobe\Acrobat 7.0\Acrobat\Acrobat.exe"
SET_COMMAND_CONTEXT INT mainwindowxcoord 0
SET_COMMAND_CONTEXT INT mainwindowycoord 0
SET_COMMAND_CONTEXT INT mainwindowheight 400
SET_COMMAND_CONTEXT INT mainwindowwidth 200
SET_PREFERENCE flowvendor Foundation_iSE
SET_PREFERENCE vhdlsim True
SET_PREFERENCE verilogsim True
SET_PREFERENCE workingdirectory F:\hawaii_f\ise\spi\spi_controller\tmp
SET_PREFERENCE speedgrade -5
SET_PREFERENCE simulationfiles Structural
SET_PREFERENCE asysymbol True
SET_PREFERENCE addpads False
SET_PREFERENCE outputdirectory F:\hawaii_f\ise\spi\spi_controller
SET_PREFERENCE device xc3s1200e
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE foundationsym False
SET_PREFERENCE package fg400
SET_PREFERENCE createndf False
SET_PREFERENCE designentry VHDL
SET_PREFERENCE devicefamily spartan3e
SET_PREFERENCE formalverification False
SET_PREFERENCE removerpms False
SET_SIM_PARAMETER c_src_status_addr 1
SET_SIM_PARAMETER c_src_clk_dist 1
SET_SIM_PARAMETER c_fifo_af_mode 1
SET_SIM_PARAMETER c_num_dip4_errors 4
SET_SIM_PARAMETER c_src_master_clk 1
SET_SIM_PARAMETER c_snk_clk_dist 1
SET_SIM_PARAMETER c_src_af_thres_negate 32
SET_SIM_PARAMETER c_src_init_val 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
SET_SIM_PARAMETER c_data_max_t 4096
SET_SIM_PARAMETER c_src_burst_mode 1
SET_SIM_PARAMETER c_src_af_thres_assert 32
SET_SIM_PARAMETER c_snk_init_val 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
SET_SIM_PARAMETER c_snk_clk_embedded 1
SET_SIM_PARAMETER c_snk_status_io 1
SET_SIM_PARAMETER c_src_burst_len 32
SET_SIM_PARAMETER c_num_training_sequence 4
SET_SIM_PARAMETER c_num_dip2_errors 4
SET_SIM_PARAMETER c_alpha_data 2
SET_SIM_PARAMETER c_src_init_file no_coe_file_loaded
SET_SIM_PARAMETER c_snk_af_thres_negate 32
SET_SIM_PARAMETER c_src_status_io 1
SET_SIM_PARAMETER c_src_calendar_len_m1 15
SET_SIM_PARAMETER c_src_tsclk_dist 1
SET_SIM_PARAMETER c_snk_af_thres_assert 32
SET_SIM_PARAMETER c_num_channels 16
SET_SIM_PARAMETER c_src_init_cal 0
SET_SIM_PARAMETER c_user_datawidth 32
SET_SIM_PARAMETER c_user_modwidth 2
SET_SIM_PARAMETER c_src_calendar_m_m1 0
SET_SIM_PARAMETER c_rsclk_phase 0
SET_SIM_PARAMETER c_snk_calendar_m_m1 0
SET_SIM_PARAMETER c_snk_calendar_len_m1 15
SET_SIM_PARAMETER c_snk_init_cal 0
SET_PARAMETER number_of_channels 16
SET_PARAMETER source_length_of_calendar_sequence 16
SET_PARAMETER sink_almost_full_assert 32
SET_PARAMETER sink_status_io LVDS_Status_IO
SET_PARAMETER source_init_file_name no_coe_file_loaded
SET_PARAMETER sink_iterations_of_status_sequence_before_dip2 1
SET_PARAMETER sink_clock_distribution Global_Clock
SET_PARAMETER source_number_dip2_matches 4
SET_PARAMETER source_almost_full_negate 32
SET_PARAMETER source_load_init_file false
SET_PARAMETER sink_number_of_training_sequences 4
SET_PARAMETER source_almost_full_assert 32
SET_PARAMETER source_number_of_dip2_errors 4
SET_PARAMETER sink_clock_mode Embedded_Clocking
SET_PARAMETER sink_number_of_dip4_errors 4
SET_PARAMETER number_of_data_cycles_before_training 4096
SET_PARAMETER component_name uart232
SET_PARAMETER source_clock_mode Master_Clock
SET_PARAMETER burst_mode Complete_Burst
SET_PARAMETER sink_length_of_calendar_sequence 16
SET_PARAMETER source_clock_distribution Global_Clock
SET_PARAMETER source_status_io LVDS_Status_IO
SET_PARAMETER sink_load_init_file false
SET_PARAMETER status_fifo_interface Addressable
SET_PARAMETER user_interface_data_width 32
SET_PARAMETER sink_status_alignment RStat_Changes_on_Rising_RSClk
SET_PARAMETER sink_when_fifo_almost_full Send_Satisfied_On_All_Channels
SET_PARAMETER sink_status_channel_rate Status_Channel_Quarter_RDClk
SET_PARAMETER tsclk_clock_distribution Global_Clock
SET_PARAMETER burst_size_in_credits 32
SET_PARAMETER sink_init_file_name no_coe_file_loaded
SET_PARAMETER sink_almost_full_negate 32
SET_PARAMETER number_of_training_patterns_during_training 2
SET_PARAMETER source_iteration_of_status_sequence_before_dip2 1
SET_CORE_CLASS com.xilinx.ip.pl4_lite_v4_2.pl4_lite_v4_2
SET_CORE_PATH E:/ISE9_2\coregen\ip\xilinx\network\com\xilinx\ip\pl4_lite_v4_2\
SET_CORE_NAME SPI-4.2 Lite
SET_CORE_VERSION 4.2