📄 usb_ohci.h
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#define PORT_RESET_CHANGE 0x00100000
static int cc_to_error[16] =
{
/* mapping of the OHCI CC status to error codes */
/* No Error */ 0,
/* CRC Error */ USB_ST_CRC_ERR,
/* Bit Stuff */ USB_ST_BIT_ERR,
/* Data Togg */ USB_ST_CRC_ERR,
/* Stall */ USB_ST_STALLED,
/* DevNotResp */ -1,
/* PIDCheck */ USB_ST_BIT_ERR,
/* UnExpPID */ USB_ST_BIT_ERR,
/* DataOver */ USB_ST_BUF_ERR,
/* DataUnder */ USB_ST_BUF_ERR,
/* reservd */ -1,
/* reservd */ -1,
/* BufferOver */ USB_ST_BUF_ERR,
/* BuffUnder */ USB_ST_BUF_ERR,
/* Not Access */ -1,
/* Not Access */ -1
};
/* ED States */
#define ED_NEW 0x00
#define ED_UNLINK 0x01
#define ED_OPER 0x02
#define ED_DEL 0x04
#define ED_URB_DEL 0x08
/* usb_ohci_ed */
struct ed
{ unsigned int hwINFO;
unsigned int hwTailP;
unsigned int hwHeadP;
unsigned int hwNextED;
struct ed *ed_prev;
unsigned char int_period;
unsigned char int_branch;
unsigned char int_load;
unsigned char int_interval;
unsigned char state;
unsigned char type;
unsigned short last_iso;
struct ed *ed_rm_list;
struct usb_device *usb_dev;
void *purb;
unsigned int unused[2];
} __attribute((aligned(16)));
typedef struct ed ed_t;
/* TD info field */
#define TD_CC 0xf0000000
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
#define TD_EC 0x0C000000
#define TD_T 0x03000000
#define TD_T_DATA0 0x02000000
#define TD_T_DATA1 0x03000000
#define TD_T_TOGGLE 0x00000000
#define TD_R 0x00040000
#define TD_DI 0x00E00000
#define TD_DI_SET(X) (((X) & 0x07)<< 21)
#define TD_DP 0x00180000
#define TD_DP_SETUP 0x00000000
#define TD_DP_IN 0x00100000
#define TD_DP_OUT 0x00080000
#define TD_ISO 0x00010000
#define TD_DEL 0x00020000
/* CC Codes */
#define TD_CC_NOERROR 0x00
#define TD_CC_CRC 0x01
#define TD_CC_BITSTUFFING 0x02
#define TD_CC_DATATOGGLEM 0x03
#define TD_CC_STALL 0x04
#define TD_DEVNOTRESP 0x05
#define TD_PIDCHECKFAIL 0x06
#define TD_UNEXPECTEDPID 0x07
#define TD_DATAOVERRUN 0x08
#define TD_DATAUNDERRUN 0x09
#define TD_BUFFEROVERRUN 0x0C
#define TD_BUFFERUNDERRUN 0x0D
#define TD_NOTACCESSED 0x0F
#define MAXPSW 1
struct td
{
unsigned int hwINFO;
unsigned int hwCBP; /* Current Buffer Pointer */
unsigned int hwNextTD; /* Next TD Pointer */
unsigned int hwBE; /* Memory Buffer End Pointer */
unsigned char unused;
unsigned char index;
struct ed *ed;
struct td *next_dl_td;
struct usb_device *usb_dev;
int transfer_len;
unsigned int data;
unsigned int unused2[2];
} __attribute((aligned(32)));
typedef struct td td_t;
#define OHCI_ED_SKIP (1 << 14)
/*
* The HCCA (Host Controller Communications Area) is a 256 byte
* structure defined in the OHCI spec. that the host controller is
* told the base address of. It must be 256-byte aligned.
*/
#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca
{ unsigned int int_table[NUM_INTS]; /* Interrupt ED table */
unsigned short frame_no; /* current frame number */
unsigned short pad1; /* set to 0 on each frame_no change */
unsigned int done_head; /* info returned for an interrupt */
unsigned char reserved_for_hc[116];//116
} __attribute((aligned(256)));
/*
* Maximum number of root hub ports.
*/
#define MAX_ROOT_PORTS 2 /* maximum OHCI root hub ports 15*/
/*
* This is the structure of the OHCI controller's memory mapped I/O
* region. This is Memory Mapped I/O. You must use the readl() and
* writel() macros defined in asm/io.h to access these!!
*/
struct ohci_regs
{ /* control and status registers */
unsigned int revision;
unsigned int control;
unsigned int cmdstatus;
unsigned int intrstatus;
unsigned int intrenable;
unsigned int intrdisable;
/* memory pointers */
unsigned int hcca;
unsigned int ed_periodcurrent;
unsigned int ed_controlhead;
unsigned int ed_controlcurrent;
unsigned int ed_bulkhead;
unsigned int ed_bulkcurrent;
unsigned int donehead;
/* frame counters */
unsigned int fminterval;
unsigned int fmremaining;
unsigned int fmnumber;
unsigned int periodicstart;
unsigned int lsthresh;
/* Root hub ports */
struct ohci_roothub_regs
{ unsigned int a;
unsigned int b;
unsigned int status;
unsigned int portstatus[MAX_ROOT_PORTS];
} roothub;
} __attribute((aligned(32)));
/* Virtual Root HUB */
struct virt_root_hub
{
int devnum; /* Address of Root Hub endpoint */
void *dev; /* was urb */
void *int_addr;
int send;
int interval;
};
/* urb */
#define N_URB_TD 48
typedef struct
{
ed_t *ed;
unsigned short length; /* number of tds associated with this request */
unsigned short td_cnt; /* number of tds already serviced */
struct usb_device *dev;
int state;
unsigned long pipe;
void *transfer_buffer;
int transfer_buffer_length;
int interval;
int actual_length;
int finished;
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
} urb_priv_t;
#define URB_DEL 1
/*
* This is the full ohci controller description
*
* Note how the "proper" USB information is just
* a subset of what the full implementation needs. (Linus)
*/
typedef struct ohci
{
struct ohci_hcca *hcca; /* hcca */
/*dma_addr_t hcca_dma;*/
int irq;
int disabled; /* e.g. got a UE, we're hung */
int sleeping;
unsigned long flags; /* for HC bugs */
struct ohci_regs *regs; /* OHCI controller's memory */
int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t *ed_bulktail; /* last endpoint of bulk list */
ed_t *ed_controltail; /* last endpoint of control list */
int intrstatus;
unsigned int hc_control; /* copy of the hc control reg */
struct usb_device *dev[32];
struct virt_root_hub rh;
const char *slot_name;
} ohci_t;
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
struct ohci_device
{ ed_t ed[NUM_EDS];
int ed_cnt;
};
/* endpoint */
static int ep_link(ohci_t * ohci, ed_t * ed);
static int ep_unlink(ohci_t * ohci, ed_t * ed);
static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe,
int interval, int load);
#endif
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