try.drc

带闹钟功能

Protel Design System Design Rule Check
PCB File : \资料库\MCS-51 learning broad\try.PCBDOC
Date     : 2008-3-6
Time     : 14:03:18

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.254mm) (Max=0.8mm) (Preferred=0.5mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=5.54mm) (All)
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:00