smallcore.fit.smsg

MagicSopc system with flash

    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "SDRAM_DQ[2]" is constrained to location PIN M19 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "SDRAM_DQ[1]" is constrained to location PIN M20 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|input_cell_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|input_latch_l[0]" is constrained to location LAB_X64_Y21 to improve DDIO timing
    Info: Node "SDRAM_DQ[0]" is constrained to location PIN N20 to improve DDIO timing
Info: Starting register packing
Info: Ignoring invalid fast I/O register assignments
Info: Finished register packing: elapsed time is 00:00:04
    Extra Info: Packed 91 registers into blocks of type I/O
    Extra Info: Created 15 register duplicates
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 15 total pin(s) used --  49 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 26 total pin(s) used --  37 pins available
        Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 15 total pin(s) used --  41 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  57 pins available
        Info: I/O bank number 5 uses 1.25V VREF pins and has 2.50V VCCIO pins. 41 total pin(s) used --  24 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  58 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  58 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  55 pins available
Warning: Ignored I/O standard assignments to the following nodes
    Warning: Ignored I/O standard assignment to node "SDRAM_CLK[0]"
    Warning: Ignored I/O standard assignment to node "SDRAM_cke[0]"
    Warning: Ignored I/O standard assignment to node "SDRAM_cs_n[0]"
    Warning: Ignored I/O standard assignment to node "SDRAM_nCLK[0]"
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "SDRAM_dm[0]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dm[1]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[0]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[10]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[11]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[12]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[13]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[14]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[15]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[1]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[2]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[3]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[4]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[5]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[6]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[7]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[8]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dq[9]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dqs[0]" is assigned to location or region, but does not exist in design
    Warning: Node "SDRAM_dqs[1]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:03
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:11
Info: Estimated most critical path is register to register delay of 12.353 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X28_Y16; Fanout = 4; REG Node = 'nios2e_2C35:inst1|cpu:the_cpu|W_alu_result[15]'
    Info: 2: + IC(0.511 ns) + CELL(0.370 ns) = 0.881 ns; Loc. = LAB_X28_Y16; Fanout = 1; COMB Node = 'nios2e_2C35:inst1|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~363'
    Info: 3: + IC(1.568 ns) + CELL(0.370 ns) = 2.819 ns; Loc. = LAB_X32_Y19; Fanout = 3; COMB Node = 'nios2e_2C35:inst1|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~365'
    Info: 4: + IC(0.161 ns) + CELL(0.651 ns) = 3.631 ns; Loc. = LAB_X32_Y19; Fanout = 24; COMB Node = 'nios2e_2C35:inst1|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module'
    Info: 5: + IC(0.161 ns) + CELL(0.650 ns) = 4.442 ns; Loc. = LAB_X32_Y19; Fanout = 36; COMB Node = 'nios2e_2C35:inst1|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_grant_vector[1]~61'
    Info: 6: + IC(1.355 ns) + CELL(0.206 ns) = 6.003 ns; Loc. = LAB_X33_Y22; Fanout = 33; COMB Node = 'nios2e_2C35:inst1|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[6]~120'
    Info: 7: + IC(1.356 ns) + CELL(0.202 ns) = 7.561 ns; Loc. = LAB_X32_Y19; Fanout = 5; COMB Node = 'nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~67'
    Info: 8: + IC(0.188 ns) + CELL(0.624 ns) = 8.373 ns; Loc. = LAB_X32_Y19; Fanout = 11; COMB Node = 'nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal1~28'
    Info: 9: + IC(1.292 ns) + CELL(0.650 ns) = 10.315 ns; Loc. = LAB_X35_Y18; Fanout = 2; COMB Node = 'nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[21]~1318'
    Info: 10: + IC(0.748 ns) + CELL(0.370 ns) = 11.433 ns; Loc. = LAB_X34_Y18; Fanout = 1; COMB Node = 'nios2e_2C35:inst1|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~3043'
    Info: 11: + IC(0.161 ns) + CELL(0.651 ns) = 12.245 ns; Loc. = LAB_X34_Y18; Fanout = 1; COMB Node = 'nios2e_2C35:inst1|cpu:the_cpu|av_ld_byte2_data[5]~18'
    Info: 12: + IC(0.000 ns) + CELL(0.108 ns) = 12.353 ns; Loc. = LAB_X34_Y18; Fanout = 2; REG Node = 'nios2e_2C35:inst1|cpu:the_cpu|av_ld_byte2_data[5]'