smallcore.map.rpt

MagicSopc system with flash

; Total registers                    ; N/A until Partition Merge               ;
; Total pins                         ; N/A until Partition Merge               ;
; Total virtual pins                 ; N/A until Partition Merge               ;
; Total memory bits                  ; N/A until Partition Merge               ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge               ;
; Total PLLs                         ; N/A until Partition Merge               ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C8       ;                    ;
; Top-level entity name                                              ; SmallCore          ; SmallCore          ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                  ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                   ;
+----------------------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; File Name with User-Entered Path                         ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                           ;
+----------------------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; SmallCore.bdf                                            ; yes             ; User Block Diagram/Schematic File  ; D:/MagicSOPC_SOPC_TEST/SmallCore_flash/SmallCore.bdf                   ;
; C:/altera/70/ip/ddr_ddr2_sdram/lib/auk_ddr_functions.vhd ; yes             ; Encrypted User VHDL File           ; C:/altera/70/ip/ddr_ddr2_sdram/lib/auk_ddr_functions.vhd               ;
; nios2e_2C35.v                                            ; yes             ; Other                              ; D:/MagicSOPC_SOPC_TEST/SmallCore_flash/nios2e_2C35.v                   ;
; cpu.v                                                    ; yes             ; Encrypted File                     ; D:/MagicSOPC_SOPC_TEST/SmallCore_flash/cpu.v                           ;
; cpu_test_bench.v                                         ; yes             ; Other                              ; D:/MagicSOPC_SOPC_TEST/SmallCore_flash/cpu_test_bench.v                ;