smallcore.fit.rpt

MagicSopc system with flash

; Quartus II Version                 ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name                      ; SmallCore                               ;
; Top-level Entity Name              ; SmallCore                               ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C35F672C8                            ;
; Timing Models                      ; Final                                   ;
; Total logic elements               ; 2,566 / 33,216 ( 8 % )                  ;
;     Total combinational functions  ; 2,209 / 33,216 ( 7 % )                  ;
;     Dedicated logic registers      ; 1,568 / 33,216 ( 5 % )                  ;
; Total registers                    ; 1659                                    ;
; Total pins                         ; 98 / 475 ( 21 % )                       ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 11,392 / 483,840 ( 2 % )                ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                          ;
; Total PLLs                         ; 1 / 4 ( 25 % )                          ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                          ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                 ; Setting                        ; Default Value                  ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                 ; EP2C35F672C8                   ;                                ;
; Fit Attempts to Skip                                   ; 0                              ; 0.0                            ;
; Optimize Fast-Corner Timing                            ; On                             ; Off                            ;
; Fitter Effort                                          ; Fast Fit                       ; Auto Fit                       ;
; Always Enable Input Buffers                            ; Off                            ; Off                            ;
; Router Timing Optimization Level                       ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                            ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                               ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                   ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; PowerPlay Power Optimization                           ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                        ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                             ; On                             ;
; Limit to One Fitting Attempt                           ; Off                            ; Off                            ;
; Final Placement Optimizations                          ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                              ; 1                              ;
; PCI I/O                                                ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                     ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto                           ; Auto                           ;
; Auto Delay Chains                                      ; On                             ; On                             ;
; Auto Merge PLLs                                        ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                      ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic     ; Off                            ; Off                            ;
; Perform Register Duplication                           ; Off                            ; Off                            ;
; Perform Register Retiming                              ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                        ; Normal                         ; Normal                         ;
; Auto Global Clock                                      ; On                             ; On                             ;
; Auto Global Register Control Signals                   ; On                             ; On                             ;
; Stop After Congestion Map Generation                   ; Off                            ; Off                            ;
; Use smart compilation                                  ; Off                            ; Off                            ;
+--------------------------------------------------------+--------------------------------+--------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+--------------------------------------------------------------------------------------------------------------+------------------+
; Node                                                                                                                                    ; Action          ; Operation        ; Reason                                 ; Node Port ; Destination Node                                                                                             ; Destination Port ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+--------------------------------------------------------------------------------------------------------------+------------------+
; nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|ddr_a[0]  ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ; SDRAM_A[0]                                                                                                   ; DATAIN           ;