ddr_sdram_extraction_log2.txt

MagicSopc system with flash

    Info: Pin "flash_D[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_D[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SDRAM_CKE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SDRAM_CS_n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_nOE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_nWE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Flash_nCS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "flash_A[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LED[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LED[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LED[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LED[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LED[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LED[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LED[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LED[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir~7" is a latch
    Warning: Node "nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr~8" is a latch
found 16/64 pins
Extraction took 23823852 microseconds per iteration
Generating precompile numbers
min_paths : dq_capture 921 posten_capture 702 name {SDRAM_DQ[0]} number 0 clkctrl_capture 971 dqs_clkctrl 2464 clkctrl_resync 971 capture_resync 422 clkctrl_posten 970 postctrl_posten 662 sysclk_pin 1975
max_paths : dq_capture 2138 posten_capture 2320 name {SDRAM_DQ[9]} number 31 clkctrl_capture 1853 dqs_clkctrl 3982 clkctrl_resync 1853 capture_resync 1400 clkctrl_posten 1849 postctrl_posten 1547 sysclk_pin 4504

>>> POST_compile_mode <<<

    MESSAGE             "NOTE:     Speed Grade c8 used for analysis"
Info: Extracted data should exist as data arrays.
    MESSAGE             "NOTE:     For a 'Custom' memory device, please ensure that your chosen CL is compatible with your clock speed selection"
min dq_capture 921 922 932 933 936 937 943 946 947 948 951 952 963 964 965 966 967 972 973 974 975 976 978
min posten_capture 702 703 711 715 833 834 839 840
min name {SDRAM_DQ[0]} {SDRAM_DQ[1]} {SDRAM_DQ[2]} {SDRAM_DQ[3]} {SDRAM_DQ[4]} {SDRAM_DQ[5]} {SDRAM_DQ[6]} {SDRAM_DQ[7]} {SDRAM_DQ[0]} {SDRAM_DQ[1]} {SDRAM_DQ[2]} {SDRAM_DQ[3]} {SDRAM_DQ[4]} {SDRAM_DQ[5]} {SDRAM_DQ[6]} {SDRAM_DQ[7]} {SDRAM_DQ[8]} {SDRAM_DQ[9]} {SDRAM_DQ[10]} {SDRAM_DQ[11]} {SDRAM_DQ[12]} {SDRAM_DQ[13]} {SDRAM_DQ[14]} {SDRAM_DQ[15]} {SDRAM_DQ[8]} {SDRAM_DQ[9]} {SDRAM_DQ[10]} {SDRAM_DQ[11]} {SDRAM_DQ[12]} {SDRAM_DQ[13]} {SDRAM_DQ[14]} {SDRAM_DQ[15]}
min number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
min clkctrl_capture 971 978 981 991 994 997
min dqs_clkctrl 2464 2513
min clkctrl_resync 971 978 981 991 994 997
min capture_resync 422 423 424 426 427 428 429 430 431 432 433 434 435
min clkctrl_posten 970 994
min postctrl_posten 662 663
min sysclk_pin 1975
max dq_capture 2001 2002 2011 2012 2031 2042 2043 2051 2052 2091 2092 2102 2103 2122 2124 2125 2127 2128 2132 2134 2135 2136 2137 2138
max posten_capture 1893 1894 1908 1909 1917 1918 2248 2249 2309 2320
max name {SDRAM_DQ[0]} {SDRAM_DQ[1]} {SDRAM_DQ[2]} {SDRAM_DQ[3]} {SDRAM_DQ[4]} {SDRAM_DQ[5]} {SDRAM_DQ[6]} {SDRAM_DQ[7]} {SDRAM_DQ[0]} {SDRAM_DQ[1]} {SDRAM_DQ[2]} {SDRAM_DQ[3]} {SDRAM_DQ[4]} {SDRAM_DQ[5]} {SDRAM_DQ[6]} {SDRAM_DQ[7]} {SDRAM_DQ[8]} {SDRAM_DQ[9]} {SDRAM_DQ[10]} {SDRAM_DQ[11]} {SDRAM_DQ[12]} {SDRAM_DQ[13]} {SDRAM_DQ[14]} {SDRAM_DQ[15]} {SDRAM_DQ[8]} {SDRAM_DQ[9]} {SDRAM_DQ[10]} {SDRAM_DQ[11]} {SDRAM_DQ[12]} {SDRAM_DQ[13]} {SDRAM_DQ[14]} {SDRAM_DQ[15]}
max number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
max clkctrl_capture 1824 1831 1834 1846 1850 1853
max dqs_clkctrl 3911 3982
max clkctrl_resync 1824 1831 1834 1846 1850 1853
max capture_resync 1372 1373 1376 1377 1378 1379 1380 1381 1382 1385 1386 1387 1389 1390 1393 1397 1398 1400
max clkctrl_posten 1823 1849
max postctrl_posten 1542 1547
max sysclk_pin 4504
Info: Evaluation of Tcl script C:/altera/70/ip/ddr_ddr2_sdram/system_timing/tan_arg2.tcl was successful
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 9 warnings
    Info: Allocated 158 megabytes of memory during processing
    Info: Processing ended: Tue Jul 03 17:39:25 2007
    Info: Elapsed time: 00:00:26