smallcore.tan.summary

MagicSopc system with flash

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.591 ns
From           : altera_internal_jtag~SHIFTUSER
To             : nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[14]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : 0.907 ns
Required Time  : 6.000 ns
Actual Time    : 5.093 ns
From           : pll:inst|altpll:altpll_component|_clk0
To             : SDRAM_nCLK
From Clock     : SYS_CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : 0.300 ns
Required Time  : 1.700 ns
Actual Time    : 1.400 ns
From           : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|input_cell_h[0]
To             : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|resynched_data[13]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.051 ns
From           : altera_internal_jtag~TDIUTAP
To             : sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'pll:inst|altpll:altpll_component|_clk0'
Slack          : 0.158 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : 81.02 MHz ( period = 12.342 ns )
From           : nios2e_2C35:inst1|cpu:the_cpu|W_alu_result[19]
To             : nios2e_2C35:inst1|cpu:the_cpu|D_iw[2]
From Clock     : pll:inst|altpll:altpll_component|_clk0
To Clock       : pll:inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'pll:inst|altpll:altpll_component|_clk1'
Slack          : 6.733 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|wdata_r[7]
To             : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]
From Clock     : pll:inst|altpll:altpll_component|_clk0
To Clock       : pll:inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'SYS_CLK'
Slack          : 16.088 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 255.62 MHz ( period = 3.912 ns )
From           : delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]
To             : delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[0]
From Clock     : SYS_CLK
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 75.04 MHz ( period = 13.327 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
To             : nios2e_2C35:inst1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[14]
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'pll:inst|altpll:altpll_component|_clk0'
Slack          : 0.499 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|init_200us_done
To             : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|init_200us_done
From Clock     : pll:inst|altpll:altpll_component|_clk0
To Clock       : pll:inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'SYS_CLK'
Slack          : 1.164 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[1]
To             : delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated|safe_q[1]
From Clock     : SYS_CLK
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Clock Hold: 'pll:inst|altpll:altpll_component|_clk1'
Slack          : 3.833 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dm_out[1]
To             : nios2e_2C35:inst1|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output_cell_L[0]
From Clock     : pll:inst|altpll:altpll_component|_clk0
To Clock       : pll:inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------