📄 nios2e_2c35.v
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end
//unpredictable registered wait state incoming data, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_cpu_data_master_readdata <= 0;
else if (1)
registered_cpu_data_master_readdata <= p1_registered_cpu_data_master_readdata;
end
//registered readdata mux, which is an e_mux
assign p1_registered_cpu_data_master_readdata = ({32 {~cpu_data_master_requests_ddr_sdram_s1}} | ddr_sdram_s1_readdata_from_sa) &
({32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | jtag_uart_avalon_jtag_slave_readdata_from_sa);
//irq assign, which is an e_assign
assign cpu_data_master_irq = {1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
jtag_uart_avalon_jtag_slave_irq_from_sa,
sys_clk_timer_s1_irq_from_sa};
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_instruction_master_arbitrator (
// inputs:
clk,
cpu_instruction_master_address,
cpu_instruction_master_granted_cpu_jtag_debug_module,
cpu_instruction_master_granted_ddr_sdram_s1,
cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
cpu_instruction_master_qualified_request_ddr_sdram_s1,
cpu_instruction_master_read,
cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
cpu_instruction_master_read_data_valid_ddr_sdram_s1,
cpu_instruction_master_read_data_valid_ddr_sdram_s1_shift_register,
cpu_instruction_master_requests_cpu_jtag_debug_module,
cpu_instruction_master_requests_ddr_sdram_s1,
cpu_jtag_debug_module_readdata_from_sa,
d1_cpu_jtag_debug_module_end_xfer,
d1_ddr_sdram_s1_end_xfer,
ddr_sdram_s1_readdata_from_sa,
ddr_sdram_s1_waitrequest_n_from_sa,
reset_n,
// outputs:
cpu_instruction_master_address_to_slave,
cpu_instruction_master_readdata,
cpu_instruction_master_waitrequest
)
/* synthesis auto_dissolve = "FALSE" */ ;
output [ 24: 0] cpu_instruction_master_address_to_slave;
output [ 31: 0] cpu_instruction_master_readdata;
output cpu_instruction_master_waitrequest;
input clk;
input [ 24: 0] cpu_instruction_master_address;
input cpu_instruction_master_granted_cpu_jtag_debug_module;
input cpu_instruction_master_granted_ddr_sdram_s1;
input cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
input cpu_instruction_master_qualified_request_ddr_sdram_s1;
input cpu_instruction_master_read;
input cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
input cpu_instruction_master_read_data_valid_ddr_sdram_s1;
input cpu_instruction_master_read_data_valid_ddr_sdram_s1_shift_register;
input cpu_instruction_master_requests_cpu_jtag_debug_module;
input cpu_instruction_master_requests_ddr_sdram_s1;
input [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
input d1_cpu_jtag_debug_module_end_xfer;
input d1_ddr_sdram_s1_end_xfer;
input [ 31: 0] ddr_sdram_s1_readdata_from_sa;
input ddr_sdram_s1_waitrequest_n_from_sa;
input reset_n;
reg active_and_waiting_last_time;
reg [ 24: 0] cpu_instruction_master_address_last_time;
wire [ 24: 0] cpu_instruction_master_address_to_slave;
reg cpu_instruction_master_read_last_time;
wire [ 31: 0] cpu_instruction_master_readdata;
wire cpu_instruction_master_run;
wire cpu_instruction_master_waitrequest;
wire r_0;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_requests_cpu_jtag_debug_module) & (cpu_instruction_master_granted_cpu_jtag_debug_module | ~cpu_instruction_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~(cpu_instruction_master_read) | (1 & ~d1_cpu_jtag_debug_module_end_xfer & (cpu_instruction_master_read)))) & 1 & (cpu_instruction_master_qualified_request_ddr_sdram_s1 | cpu_instruction_master_read_data_valid_ddr_sdram_s1 | ~cpu_instruction_master_requests_ddr_sdram_s1) & (cpu_instruction_master_granted_ddr_sdram_s1 | ~cpu_instruction_master_qualified_request_ddr_sdram_s1) & ((~cpu_instruction_master_qualified_request_ddr_sdram_s1 | ~cpu_instruction_master_read | (cpu_instruction_master_read_data_valid_ddr_sdram_s1 & cpu_instruction_master_read)));
//cascaded wait assignment, which is an e_assign
assign cpu_instruction_master_run = r_0;
//optimize select-logic by passing only those address bits which matter.
assign cpu_instruction_master_address_to_slave = cpu_instruction_master_address[24 : 0];
//cpu/instruction_master readdata mux, which is an e_mux
assign cpu_instruction_master_readdata = ({32 {~cpu_instruction_master_requests_cpu_jtag_debug_module}} | cpu_jtag_debug_module_readdata_from_sa) &
({32 {~cpu_instruction_master_requests_ddr_sdram_s1}} | ddr_sdram_s1_readdata_from_sa);
//actual waitrequest port, which is an e_assign
assign cpu_instruction_master_waitrequest = ~cpu_instruction_master_run;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//cpu_instruction_master_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_address_last_time <= 0;
else if (1)
cpu_instruction_master_address_last_time <= cpu_instruction_master_address;
end
//cpu/instruction_master waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else if (1)
active_and_waiting_last_time <= cpu_instruction_master_waitrequest & (cpu_instruction_master_read);
end
//cpu_instruction_master_address matches last port_name, which is an e_process
always @(active_and_waiting_last_time or cpu_instruction_master_address or cpu_instruction_master_address_last_time)
begin
if (active_and_waiting_last_time & (cpu_instruction_master_address != cpu_instruction_master_address_last_time))
begin
$write("%0d ns: cpu_instruction_master_address did not heed wait!!!", $time);
$stop;
end
end
//cpu_instruction_master_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_instruction_master_read_last_time <= 0;
else if (1)
cpu_instruction_master_read_last_time <= cpu_instruction_master_read;
end
//cpu_instruction_master_read matches last port_name, which is an e_process
always @(active_and_waiting_last_time or cpu_instruction_master_read or cpu_instruction_master_read_last_time)
begin
if (active_and_waiting_last_time & (cpu_instruction_master_read != cpu_instruction_master_read_last_time))
begin
$write("%0d ns: cpu_instruction_master_read did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module rdv_fifo_for_cpu_data_master_to_ddr_sdram_s1_module (
// inputs:
clear_fifo,
clk,
data_in,
read,
reset_n,
sync_reset,
write,
// outputs:
data_out,
empty,
fifo_contains_ones_n,
full
)
;
output data_out;
output empty;
output fifo_contains_ones_n;
output full;
input clear_fifo;
input clk;
input data_in;
input read;
input reset_n;
input sync_reset;
input write;
wire data_out;
wire empty;
reg fifo_contains_ones_n;
wire full;
reg full_0;
reg full_1;
reg full_10;
reg full_11;
reg full_12;
reg full_13;
reg full_14;
reg full_15;
wire full_16;
reg full_2;
reg full_3;
reg full_4;
reg full_5;
reg full_6;
reg full_7;
reg full_8;
reg full_9;
reg [ 5: 0] how_many_ones;
wire [ 5: 0] one_count_minus_one;
wire [ 5: 0] one_count_plus_one;
wire p0_full_0;
wire p0_stage_0;
wire p10_full_10;
wire p10_stage_10;
wire p11_full_11;
wire p11_stage_11;
wire p12_full_12;
wire p12_stage_12;
wire p13_full_13;
wire p13_stage_13;
wire p14_full_14;
wire p14_stage_14;
wire p15_full_15;
wire p15_stage_15;
wire p1_full_1;
wire p1_stage_1;
wire p2_full_2;
wire p2_stage_2;
wire p3_full_3;
wire p3_stage_3;
wire p4_full_4;
wire p4_stage_4;
wire p5_full_5;
wire p5_stage_5;
wire p6_full_6;
wire p6_stage_6;
wire p7_full_7;
wire p7_stage_7;
wire p8_full_8;
wire p8_stage_8;
wire p9_full_9;
wire p9_stage_9;
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