upsd_xreg.c

upsd 3200序列的usb驱动

// Initialization of uPSD I/Os
//
// William Chin for uPSD3234 from ST Microelectronics
// on June 14, 2002

/*---------------------------------------------------------------------------
Copyright (c) 2002 ST Microelectronics
This example demo code is provided as is and has no warranty,
implied or otherwise.  You are free to use/modify any of the provided
code at your own risk in your applications with the expressed limitation
of liability (see below) so long as your product using the code contains
at least one uPSD products (device).

LIMITATION OF LIABILITY:   NEITHER STMicroelectronics NOR ITS VENDORS OR 
AGENTS SHALL BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
--------------------------------------------------------------------------*/

//-- Includes ----------------------------------------------------------------

#include "general.h"
#include "upsd3200.h"			// SFRs
#include "upsd_xreg.h"			// Bit definitions

//-- Variables ---------------------------------------------------------------

extern PSD_REGS UPSD_xreg;

//-- Aliases of bit IOs -------------------------------------------------------

//this is just for reference
//#define BELL	UPSD_xreg.DATAOUT_B.bits.PB0

//-- Functions ----------------------------------------------------------------

void initXREG(void) {

    /************ VM ************/
    UPSD_xreg.VM |= 0x80;
                                       // bit 7 - PIO (1=enable)
                                       // bit 4 - RD access FLASH (1=enable)
                                       // bit 3 - RD access EEPROM (1=enable)
                                       // bit 2 - PSEN access FLASH (1=enable)
                                       // bit 1 - PSEN access EEPROM (1=enable)
                                       // bit 0 - PSEN access SRAM (1=enable)

                              
    /****** power management ******/
    UPSD_xreg.PMMR0=0x38;               // power-on default = 0x00 
                                        // bit 5 - CLKIN input to MCell (1=off)
                                        // bit 4 - CLKIN input to PLD array (1=off)
                                        // bit 3 - PLD turbo mode (ZPSD only) (1=disable)
                                        // bit 1 - APD unit (1=enable)
    
    UPSD_xreg.PMMR2=0x70;               // power-on default = 0x00 
                                        // bit 6 - DBE input to PLD array (1=off)
                                        // bit 5 - ALE input to PLD array (1=off)
                                        // bit 4 - CNTL2 input to PLD array (1=off)
                                        // bit 3 - CNTL1 input to PLD array (1=off)
                                        // bit 2 - CNTL0 input to PLD array (1=off)
}