shuikong.sum

upsd3200单片机IAP的实现

***********************************************************************
                         PSDsoft Express Version 8.50
                         Summary of Design Assistant
***********************************************************************
PROJECT    : shuikong                      DATE : 03/28/2006
DEVICE     : uPSD3254BV                    TIME : 13:26:42
MCU/DSP    : uPSD32XX    
***********************************************************************

Initial setting for Program and Data Space:
===========================================

  Main PSD flash memory will reside in this space at power-up:      Data Space Only
  Secondary PSD flash memory will reside in this space at power-up: Program Space Only

Pin Definitions:
================

Pin          Signal                    Pin
Name         Name                      Type
------------ ------------------------- ------------
pa7          SMDET                     GP I/O mode 
pa6          PT_le                     External chip select - Active Hi
pa5          AD14                      Combinatorial
pa4          AD13                      Combinatorial
pa3          AD12                      Combinatorial
pa2          smclk                     Combinatorial
pa1          simclk                    Combinatorial
pa0          clkcard                   Logic or address
pb7          rd_cpld                   External chip select - Active-Lo
pb6          USB_INT                   GP I/O mode 
pb5          CS1                       External chip select - Active Hi
pb4          K_DI                      GP I/O mode with pin enable
pb3          VFD_STB                   GP I/O mode with pin enable
pb2          VFD_SCK                   GP I/O mode with pin enable
pb1          VFD_DO                    GP I/O mode with pin enable
pb0          EN_LCD                    GP I/O mode 
pc7          SMC8                      GP I/O mode 
tdo          tdo                       Dedicated JTAG - TDO
tdi          tdi                       Dedicated JTAG - TDI
pc4          CEFS                      External chip select - Active-Lo
pc3          SRAMCS                    External chip select - Active-Lo
pc2          CSPLD                     External chip select - Active-Lo
tck          tck                       Dedicated JTAG - TCK
tms          tms                       Dedicated JTAG - TMS
pd2          WIND                      GP I/O mode 
pd1          USB_CS                    External chip select - Active-Lo
ale          ale                       ALE output  
p4.7         A19                       GP I/O mode 
p4.6         A18                       GP I/O mode 
p4.5         A17                       GP I/O mode 
p4.4         A16                       GP I/O mode 
p4.3         A15                       GP I/O mode 
p4.2         SM_DET                    GP I/O mode 
p4.1         SMIOCLK                   GP I/O mode 
p4.0         SMC4                      GP I/O mode 
p3.4         HOME_P                    GP I/O mode 
p3.1         UART1_TxD                 UART1 TxD   
p3.0         UART1_RxD                 UART1 RxD   
p1.7         BUSY                      GP I/O mode 
p1.6         PAPER                     GP I/O mode 
p1.5         MARK                      GP I/O mode 
p1.4         TH_SIG                    GP I/O mode 
p1.3         UART2_TxD                 UART2 TxD   
p1.2         UART2_RxD                 UART2 RxD   
a11          a11                       Address line
a10          a10                       Address line
a9           a9                        Address line
a8           a8                        Address line
ad7          a7                        Data/Address line
ad6          a6                        Data/Address line
ad5          a5                        Data/Address line
ad4          a4                        Data/Address line
ad3          a3                        Data/Address line
ad2          a2                        Data/Address line
ad1          a1                        Data/Address line
ad0          a0                        Data/Address line
_Reset_In    _Reset_In                 Reset In    
Vref         VREF                      VREF input  
_rd          _rd                       Bus control output
_psen        _psen                     Bus control output
_wr          _wr                       Bus control output
Xtal1        Xtal1                     Xtal1       
Xtal2        Xtal2                     Xtal2       

User defined nodes:
===================

Node         Node
Name         Type
------------ ------------
CNT1         D-type register
CNT0         D-type register
CNT2         D-type register

Page Register settings:
=======================

pgr0 is used for paging
pgr1 is used for paging
pgr2 is used for paging
pgr3 is used for logic, signal name: BOOT
pgr4 is used for logic, signal name: UPDATA
pgr5 is used for logic, signal name: FLSAH
pgr6 is used for logic, signal name: PGR6
pgr7 is used for logic, signal name: SRAM

Equations:
==========

rs0 = ((address >= ^h8200) & (address <= ^hFFFF));
csiop = ((address >= ^h8000) & (address <= ^h80FF));
fs0 = ((address >= ^h0000) & (address <= ^h7FFF) & (!_psen))
     # ((page == 0) & (address >= ^h0000) & (address <= ^h7FFF) & (UPDATA));
fs1 = ((page == 0) & (address >= ^h8000) & (address <= ^hFFFF) & (!_psen))
     # ((page == 1) & (address >= ^h0000) & (address <= ^h7FFF) & (UPDATA));
fs2 = ((page == 1) & (address >= ^h8000) & (address <= ^hFFFF) & (!_psen))
     # ((page == 2) & (address >= ^h0000) & (address <= ^h7FFF) & (UPDATA));
fs3 = ((page == 2) & (address >= ^h8000) & (address <= ^hFFFF) & (!_psen))
     # ((page == 3) & (address >= ^h0000) & (address <= ^h7FFF) & (UPDATA));
fs4 = ((page == 3) & (address >= ^h8000) & (address <= ^hFFFF) & (!_psen))
     # ((page == 4) & (address >= ^h0000) & (address <= ^h7FFF) & (UPDATA));
fs5 = ((page == 4) & (address >= ^h8000) & (address <= ^hFFFF) & (!_psen))
     # ((page == 5) & (address >= ^h0000) & (address <= ^h7FFF) & (UPDATA));
fs6 = ((page == 5) & (address >= ^h8000) & (address <= ^hFFFF) & (!_psen))
     # ((page == 6) & (address >= ^h0000) & (address <= ^h7FFF) & (UPDATA));
fs7 = ((page == 6) & (address >= ^h8000) & (address <= ^hFFFF) & (!_psen))
     # ((page == 7) & (address >= ^h0000) & (address <= ^h7FFF) & (UPDATA));
csboot0 = ((address >= ^h0000) & (address <= ^h1FFF) & (!_psen));
csboot1 = ((address >= ^h2000) & (address <= ^h3FFF) & (!_psen));
csboot2 = ((address >= ^h4000) & (address <= ^h5FFF) & (!_psen));
csboot3 = ((address >= ^h6000) & (address <= ^h7FFF) & (!_psen));
PT_le = ((address >= ^h8112) & (address <= ^h8112) & (!_wr&PGR6));
! rd_cpld = ((address >= ^h8110) & (address <= ^h8110) & (PGR6));
CS1 = ((address >= ^h8113) & (address <= ^h8113) & (!_wr&PGR6));
! CEFS = ((address >= ^h0000) & (address <= ^h7FFF) & (!_rd & FLSAH))
     # ((address >= ^h0000) & (address <= ^h7FFF) & (!_wr & FLSAH));
! SRAMCS = ((address >= ^h0000) & (address <= ^h7FFF) & (!_wr & SRAM))
     # ((address >= ^h0000) & (address <= ^h7FFF) & (!_rd & SRAM));
! CSPLD = ((address >= ^h8100) & (address <= ^h8107));
! USB_CS = ((address >= ^h8115) & (address <= ^h8115) & (PGR6));
AD14 = a14;
AD14.oe = Vcc ;
AD13 = a13;
AD13.oe = Vcc;
AD12 = a12;
AD12.oe = Vcc;
smclk = !CNT2;
smclk.oe = Vcc;
simclk = !CNT2;
simclk.oe =  Vcc;
K_DI.oe = Vcc;
VFD_STB.oe = Vcc;
VFD_SCK.oe = Vcc;
VFD_DO.oe = Vcc;
CNT1 := !CNT1 & CNT0;
CNT1.ck = !clkcard;
CNT1.re = Gnd;
CNT1.pr = Gnd;
CNT0 := !CNT1 & !CNT0;
CNT0.ck = !clkcard;
CNT0.re = Gnd;
CNT0.pr = Gnd;
CNT2 := !CNT2&CNT1;
CNT2.ck = CNT1;
CNT2.re = Gnd;
CNT2.pr = Gnd;