prev_cmp_qiangdaqi.tan.qmsg

实现n路抢答功能

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 5 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "data\[4\] " "Info: Assuming node \"data\[4\]\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "data\[4\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "data\[5\] " "Info: Assuming node \"data\[5\]\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "data\[5\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "data\[7\] " "Info: Assuming node \"data\[7\]\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "data\[7\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "data\[6\] " "Info: Assuming node \"data\[6\]\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "data\[6\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "data\[0\] " "Info: Assuming node \"data\[0\]\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "data\[0\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "data\[1\] " "Info: Assuming node \"data\[1\]\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "data\[1\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "data\[2\] " "Info: Assuming node \"data\[2\]\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "data\[2\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "data\[3\] " "Info: Assuming node \"data\[3\]\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 10 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "data\[3\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk2 " "Info: Assuming node \"clk2\" is an undefined clock" {  } { { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "17 " "Warning: Found 17 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "qiangda:u2\|cout " "Info: Detected ripple clock \"qiangda:u2\|cout\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "qiangda:u2\|cout~237 " "Info: Detected gated clock \"qiangda:u2\|cout~237\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|cout~237" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "qiangda:u2\|Mux6~35 " "Info: Detected gated clock \"qiangda:u2\|Mux6~35\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 16 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|Mux6~35" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "qiangda:u2\|q\[3\]~257 " "Info: Detected gated clock \"qiangda:u2\|q\[3\]~257\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|q\[3\]~257" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "qiangda:u2\|Mux1~278 " "Info: Detected gated clock \"qiangda:u2\|Mux1~278\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 16 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|Mux1~278" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "qiangda:u2\|cout~235 " "Info: Detected gated clock \"qiangda:u2\|cout~235\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|cout~235" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "qiangda:u2\|q\[3\]~256 " "Info: Detected gated clock \"qiangda:u2\|q\[3\]~256\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|q\[3\]~256" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "qiangda:u2\|Mux5~68 " "Info: Detected gated clock \"qiangda:u2\|Mux5~68\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 16 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|Mux5~68" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "qiangda:u2\|q\[3\]~255 " "Info: Detected gated clock \"qiangda:u2\|q\[3\]~255\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 12 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|q\[3\]~255" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u3\|t1 " "Info: Detected ripple clock \"cnt10:u3\|t1\" as buffer" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 16 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u3\|t1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u3\|t2 " "Info: Detected ripple clock \"cnt10:u3\|t2\" as buffer" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 17 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u3\|t2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "qiangda:u2\|cout~238 " "Info: Detected gated clock \"qiangda:u2\|cout~238\" as buffer" {  } { { "qiangda.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangda.vhd" 7 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "qiangda:u2\|cout~238" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sel0:u1\|t2 " "Info: Detected ripple clock \"sel0:u1\|t2\" as buffer" {  } { { "sel0.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/sel0.vhd" 11 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "sel0:u1\|t2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sel0:u1\|t1 " "Info: Detected ripple clock \"sel0:u1\|t1\" as buffer" {  } { { "sel0.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/sel0.vhd" 10 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "sel0:u1\|t1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "sel0:u1\|din " "Info: Detected gated clock \"sel0:u1\|din\" as buffer" {  } { { "sel0.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/sel0.vhd" 9 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "sel0:u1\|din" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "cnt10:u3\|temp " "Info: Detected gated clock \"cnt10:u3\|temp\" as buffer" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 18 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u3\|temp" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "cnt10:u3\|clk1 " "Info: Detected gated clock \"cnt10:u3\|clk1\" as buffer" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 19 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u3\|clk1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt10:u3\|q1\[1\] register cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 114.94 MHz 8.7 ns Internal " "Info: Clock \"clk\" has Internal fmax of 114.94 MHz between source register \"cnt10:u3\|q1\[1\]\" and destination register \"cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]\" (period= 8.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest register register " "Info: + Longest register to register delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt10:u3\|q1\[1\] 1 REG LC3_E2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_E2; Fanout = 6; REG Node = 'cnt10:u3\|q1\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt10:u3|q1[1] } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 2.000 ns cnt10:u3\|Equal1~30 2 COMB LC2_E2 2 " "Info: 2: + IC(0.300 ns) + CELL(1.700 ns) = 2.000 ns; Loc. = LC2_E2; Fanout = 2; COMB Node = 'cnt10:u3\|Equal1~30'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { cnt10:u3|q1[1] cnt10:u3|Equal1~30 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.400 ns) 4.300 ns cnt10:u3\|process0~0 3 COMB LC1_E1 4 " "Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 4.300 ns; Loc. = LC1_E1; Fanout = 4; COMB Node = 'cnt10:u3\|process0~0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { cnt10:u3|Equal1~30 cnt10:u3|process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 6.200 ns cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~50 4 COMB LC3_E1 7 " "Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 6.200 ns; Loc. = LC3_E1; Fanout = 7; COMB Node = 'cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { cnt10:u3|process0~0 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 7.600 ns cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 5 REG LC6_E1 6 " "Info: 5: + IC(0.300 ns) + CELL(1.100 ns) = 7.600 ns; Loc. = LC6_E1; Fanout = 6; REG Node = 'cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns ( 76.32 % ) " "Info: Total cell delay = 5.800 ns ( 76.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 23.68 % ) " "Info: Total interconnect delay = 1.800 ns ( 23.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { cnt10:u3|q1[1] cnt10:u3|Equal1~30 cnt10:u3|process0~0 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { cnt10:u3|q1[1] {} cnt10:u3|Equal1~30 {} cnt10:u3|process0~0 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.300ns 0.900ns 0.300ns 0.300ns } { 0.000ns 1.700ns 1.400ns 1.600ns 1.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_126 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 3.500 ns cnt10:u3\|clk1 2 COMB LC1_E3 9 " "Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 3.500 ns; Loc. = LC1_E3; Fanout = 9; COMB Node = 'cnt10:u3\|clk1'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk cnt10:u3|clk1 } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 7.000 ns cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 3 REG LC6_E1 6 " "Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC6_E1; Fanout = 6; REG Node = 'cnt10:u3\|lpm_counter:q2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 48.57 % ) " "Info: Total cell delay = 3.400 ns ( 48.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 51.43 % ) " "Info: Total interconnect delay = 3.600 ns ( 51.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { clk {} clk~out {} cnt10:u3|clk1 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 0.100ns 3.500ns } { 0.000ns 2.000ns 1.400ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_126 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 3.500 ns cnt10:u3\|clk1 2 COMB LC1_E3 9 " "Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 3.500 ns; Loc. = LC1_E3; Fanout = 9; COMB Node = 'cnt10:u3\|clk1'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk cnt10:u3|clk1 } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 7.000 ns cnt10:u3\|q1\[1\] 3 REG LC3_E2 6 " "Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC3_E2; Fanout = 6; REG Node = 'cnt10:u3\|q1\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 48.57 % ) " "Info: Total cell delay = 3.400 ns ( 48.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 51.43 % ) " "Info: Total interconnect delay = 3.600 ns ( 51.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { clk {} clk~out {} cnt10:u3|clk1 {} cnt10:u3|q1[1] {} } { 0.000ns 0.000ns 0.100ns 3.500ns } { 0.000ns 2.000ns 1.400ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { clk {} clk~out {} cnt10:u3|clk1 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 0.100ns 3.500ns } { 0.000ns 2.000ns 1.400ns 0.000ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { clk {} clk~out {} cnt10:u3|clk1 {} cnt10:u3|q1[1] {} } { 0.000ns 0.000ns 0.100ns 3.500ns } { 0.000ns 2.000ns 1.400ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "cnt10.vhd" "" { Text "E:/wubangqiang/VHDL/qiangdaqi/cnt10.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { cnt10:u3|q1[1] cnt10:u3|Equal1~30 cnt10:u3|process0~0 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { cnt10:u3|q1[1] {} cnt10:u3|Equal1~30 {} cnt10:u3|process0~0 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~50 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.300ns 0.900ns 0.300ns 0.300ns } { 0.000ns 1.700ns 1.400ns 1.600ns 1.100ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk cnt10:u3|clk1 cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { clk {} clk~out {} cnt10:u3|clk1 {} cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 0.100ns 3.500ns } { 0.000ns 2.000ns 1.400ns 0.000ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { clk cnt10:u3|clk1 cnt10:u3|q1[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { clk {} clk~out {} cnt10:u3|clk1 {} cnt10:u3|q1[1] {} } { 0.000ns 0.000ns 0.100ns 3.500ns } { 0.000ns 2.000ns 1.400ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}