sel0.vhd

来自「实现n路抢答功能」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sel0 is port(sel : in std_logic;
                    q   : out std_logic_vector(1 downto 0);
                    clk2: in std_logic);
end;
architecture one of sel0 is
 signal din: std_logic;
 signal t1 : std_logic;
 signal t2 : std_logic;
 begin 
 process (clk2)
 begin
  if rising_edge(clk2) then 
     t1<=sel;
     t2<=t1;
    else 
    t1<=t1;
    t2<=t2;
   end if;
end process;
 din<=(not t1)and t2;

 process(din)
 variable temp : integer range 0 to 2;
  begin
    if rising_edge(din)  then
    if temp=2 then temp:=0;
   else  temp:=temp+1;
    end if;
   end if;
  case temp is
        when 0 => q<="00";
        when 1 => q<="01";
        when 2 => q<="10";
        when others=> q<=NULL;
  end case;
  end process;
end;