📄 qiangdaqi.map.rpt
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------+
; |qiangdaqi ; 63 (3) ; 18 ; 0 ; 31 ; 45 (3) ; 5 (0) ; 13 (0) ; 4 (0) ; 0 (0) ; |qiangdaqi ;
; |cnt10:u3| ; 33 (28) ; 14 ; 0 ; 0 ; 19 (18) ; 3 (3) ; 11 (7) ; 4 (0) ; 0 (0) ; |qiangdaqi|cnt10:u3 ;
; |lpm_counter:q2_rtl_0| ; 5 (0) ; 4 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; 0 (0) ; |qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; 4 (4) ; 0 (0) ; |qiangdaqi|cnt10:u3|lpm_counter:q2_rtl_0|alt_counter_f10ke:wysi_counter ;
; |qiangda:u2| ; 22 (22) ; 0 ; 0 ; 0 ; 22 (22) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |qiangdaqi|qiangda:u2 ;
; |sel0:u1| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 2 (2) ; 2 (2) ; 0 (0) ; 0 (0) ; |qiangdaqi|sel0:u1 ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------+---+
; Latch Name ; ;
+-----------------------------------------------+---+
; qiangda:u2|q[0] ; ;
; qiangda:u2|q[1] ; ;
; qiangda:u2|q[2] ; ;
; qiangda:u2|q[3] ; ;
; qiangda:u2|cout ; ;
; Number of user-specified and inferred latches ; 5 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 18 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 3 ;
; Number of registers using Asynchronous Load ; 9 ;
; Number of registers using Clock Enable ; 3 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; cnt10:u3|t4 ; 2 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: cnt10:u3|lpm_counter:q2_rtl_0 ;
+------------------------+-------------------+-----------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-----------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; DOWN ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/wubangqiang/VHDL/qiangdaqi/qiangdaqi.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Wed Jul 16 10:34:08 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi
Info: Found 2 design units, including 1 entities, in source file cnt10.vhd
Info: Found design unit 1: cnt10-one
Info: Found entity 1: cnt10
Info: Found 2 design units, including 1 entities, in source file qiangda.vhd
Info: Found design unit 1: qiangda-one
Info: Found entity 1: qiangda
Info: Found 2 design units, including 1 entities, in source file qiangdaqi.vhd
Info: Found design unit 1: qiangdaqi-one
Info: Found entity 1: qiangdaqi
Info: Found 2 design units, including 1 entities, in source file sel0.vhd
Info: Found design unit 1: sel0-one
Info: Found entity 1: sel0
Info: Elaborating entity "qiangdaqi" for the top level hierarchy
Info: Elaborating entity "sel0" for hierarchy "sel0:u1"
Warning (10492): VHDL Process Statement warning at sel0.vhd(19): signal "t1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at sel0.vhd(20): signal "t2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at sel0.vhd(37): OTHERS choice is never selected
Info: Elaborating entity "qiangda" for hierarchy "qiangda:u2"
Warning (10492): VHDL Process Statement warning at qiangda.vhd(17): signal "cout" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at qiangda.vhd(30): signal "q" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at qiangda.vhd(30): signal "cout" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at qiangda.vhd(13): signal or variable "cout" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "cout" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at qiangda.vhd(13): signal or variable "q" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "q" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "cnt10" for hierarchy "cnt10:u3"
Warning (10492): VHDL Process Statement warning at cnt10.vhd(85): signal "clk3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt10:u3|q2[0]~8"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Duplicate registers merged to single register
Info: Duplicate register "cnt10:u3|t2" merged to single register "cnt10:u3|t6"
Warning: Latch qiangda:u2|q[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data[1]
Warning: Latch qiangda:u2|q[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data[0]
Warning: Latch qiangda:u2|q[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data[0]
Warning: Latch qiangda:u2|q[3] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data[1]
Warning: Latch qiangda:u2|cout has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal data[4]
Info: Registers with preset signals will power-up high
Info: Implemented 94 device resources after synthesis - the final resource count might be different
Info: Implemented 14 input pins
Info: Implemented 17 output pins
Info: Implemented 63 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
Info: Processing ended: Wed Jul 16 10:34:13 2008
Info: Elapsed time: 00:00:06
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