dtom.vhd

实现n路抢答功能

library ieee;
use ieee.std_logic_1164.all;
entity dtom is port(
                   din : in std_logic;
                   qb  :out std_logic;
                   clk2 : in std_logic);
end ;
architecture one of dtom is
  signal t1,t2: std_logic ;
   begin 
       process(clk2)
        begin
       if rising_edge(clk2) then
         t1<=din;
         t2<=t1;
        else 
         t2<=t2;
         t1<=t1;
         end if;
       end process;
         qb<=t1 or t2;
end;