pcb_project1.nsx

64*16点阵

PCB_PROJECT1
*SPICE Netlist generated by Advanced Sim server on 2008-8-1 15:57:53

*Add Node Bridge Data
ADVB1 [NetU1_CLK$DV NetU2_CLK$DV NetU3_CLK$DV NetU8_16$DV NetU8_26$DV]
+ [NetU1_CLK NetU2_CLK NetU3_CLK NetU8_16 NetU8_26] dav_mod
ADVB2 [0 VCC][GND$AD VCC$AD] adc_mod
ADVB3 [VCC$DA][VCC] dac_mod
ADVB4 [NetU8_27$DV NetU8_28$DV][NetU8_27 NetU8_28] dav_mod
.model adc_mod xadc
.model dac_mod xdac
.model dav_mod xdav

*Add Digital Supply(s)
V_VCC VCC 0 5.000

*Schematic Netlist:
C1 0 NetC1_2 30pF
C2 0 NetC2_2 30pF
C3 +5 NetC3_2 10uF
C4 0 NetC4_2 0.1uF
C5 +5 NetC5_2 0.1uF
C6 0 +5 0.1uF
C7 NetC7_1 NetC7_2 0.1uF
C8 NetC8_1 NetC8_2 0.1uF
C9 +5 0 47uF
R1 NetR1_1 NetC3_2 1K
R2 NetC3_2 0 1K
R3 NetD1_A +5 47K
AUB1A [VCC$AD GND$AD NetU8_16$DV NetU8_28$DV ][VCC$DA NetU8_16$DV NetU8_28$DV
+ NetU1_CLK$DV ]NSC_74LS02
AUB2A [VCC$AD GND$AD NetU8_27$DV NetU8_16$DV ][VCC$DA NetU8_27$DV NetU8_16$DV
+ NetU2_CLK$DV ]NSC_74LS02
AUB3A [VCC$AD GND$AD NetU8_26$DV NetU8_16$DV ][VCC$DA NetU8_26$DV NetU8_16$DV
+ NetU3_CLK$DV ]NSC_74LS02
XY1 NetC1_2 NetC2_2 XTAL

.SAVE +5 0 NetC1_2 NetC2_2 NetC3_2 NetC4_2 NetC5_2 NetC7_1 NetC7_2 NetC8_1
.SAVE NetC8_2 NetD1_A NetR1_1 NetU1_CLK NetU2_CLK NetU3_CLK NetU8_16 NetU8_26 NetU8_27
.SAVE NetU8_28 VCC @C1[i] @C2[i] @C3[i] @C4[i] @C5[i] @C6[i] @C7[i] @C8[i] @C9[i]
.SAVE @R1[i] @R2[i] @R3[i] @C1[p] @C2[p] @C3[p] @C4[p] @C5[p] @C6[p] @C7[p] @C8[p]
.SAVE @C9[p] @R1[p] @R2[p] @R3[p]

*PLOT TRAN -1 1 A=+5 A=@C1[i] A=@C1[p] A=@C2[i] A=@C2[p] A=@C3[i] A=@C3[p] A=@C4[i]
*PLOT TRAN -1 1 A=@C4[p] A=@C5[i] A=@C5[p] A=@C6[i] A=@C6[p] A=@C7[i] A=@C7[p]
*PLOT TRAN -1 1 A=@C8[i] A=@C8[p] A=@C9[i] A=@C9[p] A=NetC1_2 A=NetC2_2 A=NetC3_2
*PLOT TRAN -1 1 A=NetC4_2 A=NetC5_2 A=NetC7_1 A=NetC7_2 A=NetC8_1 A=NetC8_2 A=NetD1_A
*PLOT TRAN -1 1 A=NetR1_1 A=NetU1_CLK A=NetU2_CLK A=NetU3_CLK A=NetU8_16 A=NetU8_26
*PLOT TRAN -1 1 A=NetU8_27 A=NetU8_28 A=@R1[i] A=@R1[p] A=@R2[i] A=@R2[p] A=@R3[i]
*PLOT TRAN -1 1 A=@R3[p] A=VCC
*PLOT OP -1 1 A=+5 A=@C1[i] A=@C1[p] A=@C2[i] A=@C2[p] A=@C3[i] A=@C3[p] A=@C4[i]
*PLOT OP -1 1 A=@C4[p] A=@C5[i] A=@C5[p] A=@C6[i] A=@C6[p] A=@C7[i] A=@C7[p]
*PLOT OP -1 1 A=@C8[i] A=@C8[p] A=@C9[i] A=@C9[p] A=NetC1_2 A=NetC2_2 A=NetC3_2
*PLOT OP -1 1 A=NetC4_2 A=NetC5_2 A=NetC7_1 A=NetC7_2 A=NetC8_1 A=NetC8_2 A=NetD1_A
*PLOT OP -1 1 A=NetR1_1 A=NetU1_CLK A=NetU2_CLK A=NetU3_CLK A=NetU8_16 A=NetU8_26
*PLOT OP -1 1 A=NetU8_27 A=NetU8_28 A=@R1[i] A=@R1[p] A=@R2[i] A=@R2[p] A=@R3[i]
*PLOT OP -1 1 A=@R3[p] A=VCC

*Selected Circuit Analyses:
.TRAN 2E-8 5E-6 0 2E-8
.OP

*Models and Subcircuit:
.SUBCKT XTAL 1 2
LX 1 3 1.19366209355E-1 IC=0.5M
CX 3 4 2.12206594409E-13
C0 1 2 1.3E-11
RS 4 2 7.5E+2
.ENDS XTAL

.END