📄 msp430x22x4.h
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DEFC( P2IE , P2IE_)
#define P2SEL_ (0x002E) /* Port 2 Selection */
DEFC( P2SEL , P2SEL_)
#define P2REN_ (0x002F) /* Port 2 Resistor Enable */
DEFC( P2REN , P2REN_)
/************************************************************
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
#define P3IN_ (0x0018) /* Port 3 Input */
READ_ONLY DEFC( P3IN , P3IN_)
#define P3OUT_ (0x0019) /* Port 3 Output */
DEFC( P3OUT , P3OUT_)
#define P3DIR_ (0x001A) /* Port 3 Direction */
DEFC( P3DIR , P3DIR_)
#define P3SEL_ (0x001B) /* Port 3 Selection */
DEFC( P3SEL , P3SEL_)
#define P3REN_ (0x0010) /* Port 3 Resistor Enable */
DEFC( P3REN , P3REN_)
#define P4IN_ (0x001C) /* Port 4 Input */
READ_ONLY DEFC( P4IN , P4IN_)
#define P4OUT_ (0x001D) /* Port 4 Output */
DEFC( P4OUT , P4OUT_)
#define P4DIR_ (0x001E) /* Port 4 Direction */
DEFC( P4DIR , P4DIR_)
#define P4SEL_ (0x001F) /* Port 4 Selection */
DEFC( P4SEL , P4SEL_)
#define P4REN_ (0x0011) /* Port 4 Resistor Enable */
DEFC( P4REN , P4REN_)
/************************************************************
* Timer A3
************************************************************/
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
#define TAIV_ (0x012E) /* Timer A Interrupt Vector Word */
READ_ONLY DEFW( TAIV , TAIV_)
#define TACTL_ (0x0160) /* Timer A Control */
DEFW( TACTL , TACTL_)
#define TACCTL0_ (0x0162) /* Timer A Capture/Compare Control 0 */
DEFW( TACCTL0 , TACCTL0_)
#define TACCTL1_ (0x0164) /* Timer A Capture/Compare Control 1 */
DEFW( TACCTL1 , TACCTL1_)
#define TACCTL2_ (0x0166) /* Timer A Capture/Compare Control 2 */
DEFW( TACCTL2 , TACCTL2_)
#define TAR_ (0x0170) /* Timer A */
DEFW( TAR , TAR_)
#define TACCR0_ (0x0172) /* Timer A Capture/Compare 0 */
DEFW( TACCR0 , TACCR0_)
#define TACCR1_ (0x0174) /* Timer A Capture/Compare 1 */
DEFW( TACCR1 , TACCR1_)
#define TACCR2_ (0x0176) /* Timer A Capture/Compare 2 */
DEFW( TACCR2 , TACCR2_)
/* Alternate register names */
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
#define ID1 (0x0080) /* Timer A clock input divider 1 */
#define ID0 (0x0040) /* Timer A clock input divider 0 */
#define MC1 (0x0020) /* Timer A mode control 1 */
#define MC0 (0x0010) /* Timer A mode control 0 */
#define TACLR (0x0004) /* Timer A counter clear */
#define TAIE (0x0002) /* Timer A counter interrupt enable */
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
#define CM1 (0x8000) /* Capture mode 1 */
#define CM0 (0x4000) /* Capture mode 0 */
#define CCIS1 (0x2000) /* Capture input select 1 */
#define CCIS0 (0x1000) /* Capture input select 0 */
#define SCS (0x0800) /* Capture sychronize */
#define SCCI (0x0400) /* Latched capture signal (read) */
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2 (0x0080) /* Output mode 2 */
#define OUTMOD1 (0x0040) /* Output mode 1 */
#define OUTMOD0 (0x0020) /* Output mode 0 */
#define CCIE (0x0010) /* Capture/compare interrupt enable */
#define CCI (0x0008) /* Capture input signal (read) */
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
#define COV (0x0002) /* Capture/compare overflow flag */
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
/************************************************************
* Timer B3
************************************************************/
#define __MSP430_HAS_TB3__ /* Definition to show that Module is available */
#define TBIV_ (0x011E) /* Timer B Interrupt Vector Word */
READ_ONLY DEFW( TBIV , TBIV_)
#define TBCTL_ (0x0180) /* Timer B Control */
DEFW( TBCTL , TBCTL_)
#define TBCCTL0_ (0x0182) /* Timer B Capture/Compare Control 0 */
DEFW( TBCCTL0 , TBCCTL0_)
#define TBCCTL1_ (0x0184) /* Timer B Capture/Compare Control 1 */
DEFW( TBCCTL1 , TBCCTL1_)
#define TBCCTL2_ (0x0186) /* Timer B Capture/Compare Control 2 */
DEFW( TBCCTL2 , TBCCTL2_)
#define TBR_ (0x0190) /* Timer B */
DEFW( TBR , TBR_)
#define TBCCR0_ (0x0192) /* Timer B Capture/Compare 0 */
DEFW( TBCCR0 , TBCCR0_)
#define TBCCR1_ (0x0194) /* Timer B Capture/Compare 1 */
DEFW( TBCCR1 , TBCCR1_)
#define TBCCR2_ (0x0196) /* Timer B Capture/Compare 2 */
DEFW( TBCCR2 , TBCCR2_)
#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */
#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */
#define CNTL1 (0x1000) /* Counter lenght 1 */
#define CNTL0 (0x0800) /* Counter lenght 0 */
#define TBSSEL1 (0x0200) /* Clock source 1 */
#define TBSSEL0 (0x0100) /* Clock source 0 */
#define TBCLR (0x0004) /* Timer B counter clear */
#define TBIE (0x0002) /* Timer B interrupt enable */
#define TBIFG (0x0001) /* Timer B interrupt flag */
#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */
#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */
#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
#define SHR_0 (0*0x2000u) /* Timer B Group: 0 - individually */
#define SHR_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define SHR_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define SHR_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
#define TBCLGRP_0 (0*0x2000u) /* Timer B Group: 0 - individually */
#define TBCLGRP_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define TBCLGRP_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define TBCLGRP_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
/* Additional Timer B Control Register bits are defined in Timer A */
#define CLLD1 (0x0400) /* Compare latch load source 1 */
#define CLLD0 (0x0200) /* Compare latch load source 0 */
#define SLSHR1 (0x0400) /* Compare latch load source 1 */
#define SLSHR0 (0x0200) /* Compare latch load source 0 */
#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
/************************************************************
* USCI
************************************************************/
#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */
#define UCA0CTL0_ (0x0060) /* USCI A0 Control Register 0 */
DEFC( UCA0CTL0 , UCA0CTL0_)
#define UCA0CTL1_ (0x0061) /* USCI A0 Control Register 1 */
DEFC( UCA0CTL1 , UCA0CTL1_)
#define UCA0BR0_ (0x0062) /* USCI A0 Baud Rate 0 */
DEFC( UCA0BR0 , UCA0BR0_)
#define UCA0BR1_ (0x0063) /* USCI A0 Baud Rate 1 */
DEFC( UCA0BR1 , UCA0BR1_)
#define UCA0MCTL_ (0x0064) /* USCI A0 Modulation Control */
DEFC( UCA0MCTL , UCA0MCTL_)
#define UCA0STAT_ (0x0065) /* USCI A0 Status Register */
DEFC( UCA0STAT , UCA0STAT_)
#define UCA0RXBUF_ (0x0066) /* USCI A0 Receive Buffer */
READ_ONLY DEFC( UCA0RXBUF , UCA0RXBUF_)
#define UCA0TXBUF_ (0x0067) /* USCI A0 Transmit Buffer */
DEFC( UCA0TXBUF , UCA0TXBUF_)
#define UCA0ABCTL_ (0x005D) /* USCI A0 LIN Control */
DEFC( UCA0ABCTL , UCA0ABCTL_)
#define UCA0IRTCTL_ (0x005E) /* USCI A0 IrDA Transmit Control */
DEFC( UCA0IRTCTL , UCA0IRTCTL_)
#define UCA0IRRCTL_ (0x005F) /* USCI A0 IrDA Receive Control */
DEFC( UCA0IRRCTL , UCA0IRRCTL_)
#define UCB0CTL0_ (0x0068) /* USCI B0 Control Register 0 */
DEFC( UCB0CTL0 , UCB0CTL0_)
#define UCB0CTL1_ (0x0069) /* USCI B0 Control Register 1 */
DEFC( UCB0CTL1 , UCB0CTL1_)
#define UCB0BR0_ (0x006A) /* USCI B0 Baud Rate 0 */
DEFC( UCB0BR0 , UCB0BR0_)
#define UCB0BR1_ (0x006B) /* USCI B0 Baud Rate 1 */
DEFC( UCB0BR1 , UCB0BR1_)
#define UCB0I2CIE_ (0x006C) /* USCI B0 I2C Interrupt Enable Register */
DEFC( UCB0I2CIE , UCB0I2CIE_)
#define UCB0STAT_ (0x006D) /* USCI B0 Status Register */
DEFC( UCB0STAT , UCB0STAT_)
#define UCB0RXBUF_ (0x006E) /* USCI B0 Receive Buffer */
READ_ONLY DEFC( UCB0RXBUF , UCB0RXBUF_)
#define UCB0TXBUF_ (0x006F) /* USCI B0 Transmit Buffer */
DEFC( UCB0TXBUF , UCB0TXBUF_)
#define UCB0I2COA_ (0x0118) /* USCI B0 I2C Own Address */
DEFW( UCB0I2COA , UCB0I2COA_)
#define UCB0I2CSA_ (0x011A) /* USCI B0 I2C Slave Address */
DEFW( UCB0I2CSA , UCB0I2CSA_)
// UART-Mode Bits
#define UCPEN (0x80) /* Async. Mode: Parity enable */
#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */
#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */
#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */
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