📄 at91m40800.inc
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AT91C_SF_VERSION EQU (0x1F:SHL:0) ;- (SF) Version of the chip
AT91C_SF_BIT5 EQU (0x1:SHL:5) ;- (SF) Hardwired at 0
AT91C_SF_BIT6 EQU (0x1:SHL:6) ;- (SF) Hardwired at 1
AT91C_SF_BIT7 EQU (0x1:SHL:7) ;- (SF) Hardwired at 0
AT91C_SF_NVPSIZ EQU (0xF:SHL:8) ;- (SF) Nonvolatile Program Memory Size
AT91C_SF_NVPSIZ_NONE EQU (0x0:SHL:8) ;- (SF) None
AT91C_SF_NVPSIZ_32K EQU (0x3:SHL:8) ;- (SF) 32K Bytes
AT91C_SF_NVPSIZ_64K EQU (0x5:SHL:8) ;- (SF) 64K Bytes
AT91C_SF_NVPSIZ_128K EQU (0x7:SHL:8) ;- (SF) 128K Bytes
AT91C_SF_NVPSIZ_256K EQU (0x11:SHL:8) ;- (SF) 256K Bytes
AT91C_SF_NVDSIZ EQU (0xF:SHL:12) ;- (SF) Nonvolatile Data Memory Size
AT91C_SF_NVDSIZ_NONE EQU (0x0:SHL:12) ;- (SF) None
AT91C_SF_VDSIZ EQU (0xF:SHL:16) ;- (SF) Volatile Data Memory Size
AT91C_SF_VDSIZ_NONE EQU (0x0:SHL:16) ;- (SF) None
AT91C_SF_VDSIZ_1K EQU (0x3:SHL:16) ;- (SF) 1K Bytes
AT91C_SF_VDSIZ_2K EQU (0x5:SHL:16) ;- (SF) 2K Bytes
AT91C_SF_VDSIZ_4K EQU (0x7:SHL:16) ;- (SF) 4K Bytes
AT91C_SF_VDSIZ_8K EQU (0x11:SHL:16) ;- (SF) 8K Bytes
AT91C_SF_ARCH EQU (0xFF:SHL:20) ;- (SF) Chip Architecture
AT91C_SF_ARCH_AT91x40 EQU (0x28:SHL:20) ;- (SF) AT91x40yyy
AT91C_SF_ARCH_AT91x55 EQU (0x37:SHL:20) ;- (SF) AT91x55yyy
AT91C_SF_ARCH_AT91x63 EQU (0x3F:SHL:20) ;- (SF) AT91x63yyy
AT91C_SF_NVPTYP EQU (0x7:SHL:28) ;- (SF) Nonvolatile Program Memory Type
AT91C_SF_NVPTYP_NVPTYP_M EQU (0x1:SHL:28) ;- (SF) 'M' Series or 'F' Series
AT91C_SF_NVPTYP_NVPTYP_R EQU (0x4:SHL:28) ;- (SF) 'R' Series
AT91C_SF_EXT EQU (0x1:SHL:31) ;- (SF) Extension Flag
;- -------- SF_RSR : (SF Offset: 0x8) Reset Status Information --------
AT91C_SF_RESET EQU (0xFF:SHL:0) ;- (SF) Cause of Reset
AT91C_SF_RESET_WD EQU (0x35) ;- (SF) Internal Watchdog
AT91C_SF_RESET_EXT EQU (0x6C) ;- (SF) External Pin
;- -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register --------
AT91C_SF_RAMWU EQU (0x1:SHL:0) ;- (SF) Internal Extended RAM Write Detection
;- -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register --------
AT91C_SF_AIC EQU (0x1:SHL:5) ;- (SF) AIC Protect Mode Enable
AT91C_SF_PMRKEY EQU (0xFFFF:SHL:16) ;- (SF) Protect Mode Register Key
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR External Bus Interface
;- *****************************************************************************
^ 0 ;- AT91S_EBI
EBI_CSR # 32 ;- Chip-select Register
EBI_RCR # 4 ;- Remap Control Register
EBI_MCR # 4 ;- Memory Control Register
;- -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register --------
AT91C_EBI_DBW EQU (0x3:SHL:0) ;- (EBI) Data Bus Width
AT91C_EBI_DBW_16 EQU (0x1) ;- (EBI) 16-bit data bus width
AT91C_EBI_DBW_8 EQU (0x2) ;- (EBI) 8-bit data bus width
AT91C_EBI_NWS EQU (0x7:SHL:2) ;- (EBI) Number of wait states
AT91C_EBI_NWS_1 EQU (0x0:SHL:2) ;- (EBI) 1 wait state
AT91C_EBI_NWS_2 EQU (0x1:SHL:2) ;- (EBI) 2 wait state
AT91C_EBI_NWS_3 EQU (0x2:SHL:2) ;- (EBI) 3 wait state
AT91C_EBI_NWS_4 EQU (0x3:SHL:2) ;- (EBI) 4 wait state
AT91C_EBI_NWS_5 EQU (0x4:SHL:2) ;- (EBI) 5 wait state
AT91C_EBI_NWS_6 EQU (0x5:SHL:2) ;- (EBI) 6 wait state
AT91C_EBI_NWS_7 EQU (0x6:SHL:2) ;- (EBI) 7 wait state
AT91C_EBI_NWS_8 EQU (0x7:SHL:2) ;- (EBI) 8 wait state
AT91C_EBI_WSE EQU (0x1:SHL:5) ;- (EBI) Wait State Enable
AT91C_EBI_PAGES EQU (0x3:SHL:7) ;- (EBI) Pages Size
AT91C_EBI_PAGES_1M EQU (0x0:SHL:7) ;- (EBI) 1M Byte
AT91C_EBI_PAGES_4M EQU (0x1:SHL:7) ;- (EBI) 4M Byte
AT91C_EBI_PAGES_16M EQU (0x2:SHL:7) ;- (EBI) 16M Byte
AT91C_EBI_PAGES_64M EQU (0x3:SHL:7) ;- (EBI) 64M Byte
AT91C_EBI_TDF EQU (0x7:SHL:9) ;- (EBI) Data Float Output Time
AT91C_EBI_TDF_0 EQU (0x0:SHL:9) ;- (EBI) 1 TDF
AT91C_EBI_TDF_1 EQU (0x1:SHL:9) ;- (EBI) 2 TDF
AT91C_EBI_TDF_2 EQU (0x2:SHL:9) ;- (EBI) 3 TDF
AT91C_EBI_TDF_3 EQU (0x3:SHL:9) ;- (EBI) 4 TDF
AT91C_EBI_TDF_4 EQU (0x4:SHL:9) ;- (EBI) 5 TDF
AT91C_EBI_TDF_5 EQU (0x5:SHL:9) ;- (EBI) 6 TDF
AT91C_EBI_TDF_6 EQU (0x6:SHL:9) ;- (EBI) 7 TDF
AT91C_EBI_TDF_7 EQU (0x7:SHL:9) ;- (EBI) 8 TDF
AT91C_EBI_BAT EQU (0x1:SHL:12) ;- (EBI) Byte Access Type
AT91C_EBI_CSEN EQU (0x1:SHL:13) ;- (EBI) Chip Select Enable
AT91C_EBI_BA EQU (0xFFF:SHL:20) ;- (EBI) Base Address
;- -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register --------
AT91C_EBI_RCB EQU (0x1:SHL:0) ;- (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
;- -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register --------
AT91C_EBI_ALE EQU (0x7:SHL:0) ;- (EBI) Address Line Enable
AT91C_EBI_ALE_16M EQU (0x0) ;- (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None
AT91C_EBI_ALE_8M EQU (0x4) ;- (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4
AT91C_EBI_ALE_4M EQU (0x5) ;- (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5
AT91C_EBI_ALE_2M EQU (0x6) ;- (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6
AT91C_EBI_ALE_1M EQU (0x7) ;- (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7
AT91C_EBI_DRP EQU (0x1:SHL:4) ;- (EBI)
;- *****************************************************************************
;- REGISTER ADDRESS DEFINITION FOR AT91R40008
;- *****************************************************************************
;- ========== Register definition for AIC peripheral ==========
AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector egister
AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode egister
AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command egister
;- ========== Register definition for WD peripheral ==========
AT91C_WD_SR EQU (0xFFFF800C) ;- (WD) Status Register
AT91C_WD_CMR EQU (0xFFFF8004) ;- (WD) Clock Mode Register
AT91C_WD_CR EQU (0xFFFF8008) ;- (WD) Control Register
AT91C_WD_OMR EQU (0xFFFF8000) ;- (WD) Overflow Mode Register
;- ========== Register definition for PS peripheral ==========
AT91C_PS_PCDR EQU (0xFFFF4008) ;- (PS) Peripheral Clock Disable Register
AT91C_PS_CR EQU (0xFFFF4000) ;- (PS) Control Register
AT91C_PS_PCSR EQU (0xFFFF400C) ;- (PS) Peripheral Clock Status Register
AT91C_PS_PCER EQU (0xFFFF4004) ;- (PS) Peripheral Clock Enable Register
;- ========== Register definition for PIO peripheral ==========
AT91C_PIO_MDSR EQU (0xFFFF0058) ;- (PIO) Multi-driver Status Register
AT91C_PIO_IFSR EQU (0xFFFF0028) ;- (PIO) Input Filter Status Register
AT91C_PIO_IFER EQU (0xFFFF0020) ;- (PIO) Input Filter Enable Register
AT91C_PIO_OSR EQU (0xFFFF0018) ;- (PIO) Output Status Register
AT91C_PIO_OER EQU (0xFFFF0010) ;- (PIO) Output Enable Register
AT91C_PIO_PSR EQU (0xFFFF0008) ;- (PIO) PIO Status Register
AT91C_PIO_PDSR EQU (0xFFFF003C) ;- (PIO) Pin Data Status Register
AT91C_PIO_CODR EQU (0xFFFF0034) ;- (PIO) Clear Output Data Register
AT91C_PIO_IFDR EQU (0xFFFF0024) ;- (PIO) Input Filter Disable Register
AT91C_PIO_MDER EQU (0xFFFF0050) ;- (PIO) Multi-driver Enable Register
AT91C_PIO_IMR EQU (0xFFFF0048) ;- (PIO) Interrupt Mask Register
AT91C_PIO_IER EQU (0xFFFF0040) ;- (PIO) Interrupt Enable Register
AT91C_PIO_ODSR EQU (0xFFFF0038) ;- (PIO) Output Data Status Register
AT91C_PIO_SODR EQU (0xFFFF0030) ;- (PIO) Set Output Data Register
AT91C_PIO_PER EQU (0xFFFF0000) ;- (PIO) PIO Enable Register
AT91C_PIO_MDDR EQU (0xFFFF0054) ;- (PIO) Multi-driver Disable Register
AT91C_PIO_ISR EQU (0xFFFF004C) ;- (PIO) Interrupt Status Register
AT91C_PIO_IDR EQU (0xFFFF0044) ;- (PIO) Interrupt Disable Register
AT91C_PIO_PDR EQU (0xFFFF0004) ;- (PIO) PIO Disable Register
AT91C_PIO_ODR EQU (0xFFFF0014) ;- (PIO) Output Disable Registerr
;- ========== Register definition for TC2 peripheral ==========
AT91C_TC2_IDR EQU (0xFFFE00A8) ;- (TC2) Interrupt Disable Register
AT91C_TC2_SR EQU (0xFFFE00A0) ;- (TC2) Status Register
AT91C_TC2_RB EQU (0xFFFE0098) ;- (TC2) Register B
AT91C_TC2_CV EQU (0xFFFE0090) ;- (TC2) Counter Value
AT91C_TC2_CCR EQU (0xFFFE0080) ;- (TC2) Channel Control Register
AT91C_TC2_IMR EQU (0xFFFE00AC) ;- (TC2) Interrupt Mask Register
AT91C_TC2_IER EQU (0xFFFE00A4) ;- (TC2) Interrupt Enable Register
AT91C_TC2_RC EQU (0xFFFE009C) ;- (TC2) Register C
AT91C_TC2_RA EQU (0xFFFE0094) ;- (TC2) Register A
AT91C_TC2_CMR EQU (0xFFFE0084) ;- (TC2) Channel Mode Register
;- ========== Register definition for TC1 peripheral ==========
AT91C_TC1_IDR EQU (0xFFFE0068) ;- (TC1) Interrupt Disable Register
AT91C_TC1_SR EQU (0xFFFE0060) ;- (TC1) Status Register
AT91C_TC1_RB EQU (0xFFFE0058) ;- (TC1) Register B
AT91C_TC1_CV EQU (0xFFFE0050) ;- (TC1) Counter Value
AT91C_TC1_CCR EQU (0xFFFE0040) ;- (TC1) Channel Control Register
AT91C_TC1_IMR EQU (0xFFFE006C) ;- (TC1) Interrupt Mask Register
AT91C_TC1_IER EQU (0xFFFE0064) ;- (TC1) Interrupt Enable Register
AT91C_TC1_RC EQU (0xFFFE005C) ;- (TC1) Register C
AT91C_TC1_RA EQU (0xFFFE0054) ;- (TC1) Register A
AT91C_TC1_CMR EQU (0xFFFE0044) ;- (TC1) Channel Mode Register
;- ========== Register definition for TC0 peripheral ==========
AT91C_TC0_IDR EQU (0xFFFE0028) ;- (TC0) Interrupt Disable Register
AT91C_TC0_SR EQU (0xFFFE0020) ;- (TC0) Status Register
AT91C_TC0_RB EQU (0xFFFE0018) ;- (TC0) Register B
AT91C_TC0_CV EQU (0xFFFE0010) ;- (TC0) Counter Value
AT91C_TC0_CCR EQU (0xFFFE0000) ;- (TC0) Channel Control Register
AT91C_TC0_IMR EQU (0xFFFE002C) ;- (TC0) Interrupt Mask Register
AT91C_TC0_IER EQU (0xFFFE0024) ;- (TC0) Interrupt Enable Register
AT91C_TC0_RC EQU (0xFFFE001C) ;- (TC0) Register C
AT91C_TC0_RA EQU (0xFFFE0014) ;- (TC0) Register A
AT91C_TC0_CMR EQU (0xFFFE0004) ;- (TC0) Channel Mode Register
;- ========== Register definition for TCB0 peripheral ==========
AT91C_TCB0_BCR EQU (0xFFFE00C0) ;- (TCB0) TC Block Control Register
AT91C_TCB0_BMR EQU (0xFFFE00C4) ;- (TCB0) TC Block Mode Register
;- ========== Register definition for PDC_US1 peripheral ==========
AT91C_US1_TPR EQU (0xFFFC4038) ;- (PDC_US1) Transmit Pointer Register
AT91C_US1_RPR EQU (0xFFFC4030) ;- (PDC_US1) Receive Pointer Register
AT91C_US1_TCR EQU (0xFFFC403C) ;- (PDC_US1) Transmit Counter Register
AT91C_US1_RCR EQU (0xFFFC4034) ;- (PDC_US1) Receive Counter Register
;- ========== Register definition for US1 peripheral ==========
AT91C_US1_RTOR EQU (0xFFFCC024) ;- (US1) Receiver Time-out Register
AT91C_US1_THR EQU (0xFFFCC01C) ;- (US1) Transmitter Holding Register
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