📄 at91m40800.inc
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AT91C_TC_ACPC_NONE EQU (0x0:SHL:18) ;- (TC) Effect: none
AT91C_TC_ACPC_SET EQU (0x1:SHL:18) ;- (TC) Effect: set
AT91C_TC_ACPC_CLEAR EQU (0x2:SHL:18) ;- (TC) Effect: clear
AT91C_TC_ACPC_TOGGLE EQU (0x3:SHL:18) ;- (TC) Effect: toggle
AT91C_TC_AEEVT EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA
AT91C_TC_AEEVT_NONE EQU (0x0:SHL:20) ;- (TC) Effect: none
AT91C_TC_AEEVT_SET EQU (0x1:SHL:20) ;- (TC) Effect: set
AT91C_TC_AEEVT_CLEAR EQU (0x2:SHL:20) ;- (TC) Effect: clear
AT91C_TC_AEEVT_TOGGLE EQU (0x3:SHL:20) ;- (TC) Effect: toggle
AT91C_TC_ASWTRG EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA
AT91C_TC_ASWTRG_NONE EQU (0x0:SHL:22) ;- (TC) Effect: none
AT91C_TC_ASWTRG_SET EQU (0x1:SHL:22) ;- (TC) Effect: set
AT91C_TC_ASWTRG_CLEAR EQU (0x2:SHL:22) ;- (TC) Effect: clear
AT91C_TC_ASWTRG_TOGGLE EQU (0x3:SHL:22) ;- (TC) Effect: toggle
AT91C_TC_BCPB EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB
AT91C_TC_BCPB_NONE EQU (0x0:SHL:24) ;- (TC) Effect: none
AT91C_TC_BCPB_SET EQU (0x1:SHL:24) ;- (TC) Effect: set
AT91C_TC_BCPB_CLEAR EQU (0x2:SHL:24) ;- (TC) Effect: clear
AT91C_TC_BCPB_TOGGLE EQU (0x3:SHL:24) ;- (TC) Effect: toggle
AT91C_TC_BCPC EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB
AT91C_TC_BCPC_NONE EQU (0x0:SHL:26) ;- (TC) Effect: none
AT91C_TC_BCPC_SET EQU (0x1:SHL:26) ;- (TC) Effect: set
AT91C_TC_BCPC_CLEAR EQU (0x2:SHL:26) ;- (TC) Effect: clear
AT91C_TC_BCPC_TOGGLE EQU (0x3:SHL:26) ;- (TC) Effect: toggle
AT91C_TC_BEEVT EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB
AT91C_TC_BEEVT_NONE EQU (0x0:SHL:28) ;- (TC) Effect: none
AT91C_TC_BEEVT_SET EQU (0x1:SHL:28) ;- (TC) Effect: set
AT91C_TC_BEEVT_CLEAR EQU (0x2:SHL:28) ;- (TC) Effect: clear
AT91C_TC_BEEVT_TOGGLE EQU (0x3:SHL:28) ;- (TC) Effect: toggle
AT91C_TC_BSWTRG EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB
AT91C_TC_BSWTRG_NONE EQU (0x0:SHL:30) ;- (TC) Effect: none
AT91C_TC_BSWTRG_SET EQU (0x1:SHL:30) ;- (TC) Effect: set
AT91C_TC_BSWTRG_CLEAR EQU (0x2:SHL:30) ;- (TC) Effect: clear
AT91C_TC_BSWTRG_TOGGLE EQU (0x3:SHL:30) ;- (TC) Effect: toggle
;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
AT91C_TC_COVFS EQU (0x1:SHL:0) ;- (TC) Counter Overflow
AT91C_TC_LOVRS EQU (0x1:SHL:1) ;- (TC) Load Overrun
AT91C_TC_CPAS EQU (0x1:SHL:2) ;- (TC) RA Compare
AT91C_TC_CPBS EQU (0x1:SHL:3) ;- (TC) RB Compare
AT91C_TC_CPCS EQU (0x1:SHL:4) ;- (TC) RC Compare
AT91C_TC_LDRAS EQU (0x1:SHL:5) ;- (TC) RA Loading
AT91C_TC_LDRBS EQU (0x1:SHL:6) ;- (TC) RB Loading
AT91C_TC_ETRCS EQU (0x1:SHL:7) ;- (TC) External Trigger
AT91C_TC_ETRGS EQU (0x1:SHL:16) ;- (TC) Clock Enabling
AT91C_TC_MTIOA EQU (0x1:SHL:17) ;- (TC) TIOA Mirror
AT91C_TC_MTIOB EQU (0x1:SHL:18) ;- (TC) TIOA Mirror
;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Timer Counter Interface
;- *****************************************************************************
^ 0 ;- AT91S_TCB
TCB_TC0 # 48 ;- TC Channel 0
# 16 ;- Reserved
TCB_TC1 # 48 ;- TC Channel 1
# 16 ;- Reserved
TCB_TC2 # 48 ;- TC Channel 2
# 16 ;- Reserved
TCB_BCR # 4 ;- TC Block Control Register
TCB_BMR # 4 ;- TC Block Mode Register
;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
AT91C_TCB_SYNC EQU (0x1:SHL:0) ;- (TCB) Synchro Command
;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
AT91C_TCB_TC0XC0S EQU (0x1:SHL:0) ;- (TCB) External Clock Signal 0 Selection
AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0
AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0
AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0
AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0
AT91C_TCB_TC1XC1S EQU (0x1:SHL:2) ;- (TCB) External Clock Signal 1 Selection
AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1
AT91C_TCB_TC1XC1S_NONE EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1
AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1
AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1
AT91C_TCB_TC2XC2S EQU (0x1:SHL:4) ;- (TCB) External Clock Signal 2 Selection
AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2
AT91C_TCB_TC2XC2S_NONE EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2
AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2
AT91C_TCB_TC2XC2S_TIOA2 EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Peripheral Data Controller
;- *****************************************************************************
^ 0 ;- AT91S_PDC
PDC_RPR # 4 ;- Receive Pointer Register
PDC_RCR # 4 ;- Receive Counter Register
PDC_TPR # 4 ;- Transmit Pointer Register
PDC_TCR # 4 ;- Transmit Counter Register
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Usart
;- *****************************************************************************
^ 0 ;- AT91S_USART
US_CR # 4 ;- Control Register
US_MR # 4 ;- Mode Register
US_IER # 4 ;- Interrupt Enable Register
US_IDR # 4 ;- Interrupt Disable Register
US_IMR # 4 ;- Interrupt Mask Register
US_CSR # 4 ;- Channel Status Register
US_RHR # 4 ;- Receiver Holding Register
US_THR # 4 ;- Transmitter Holding Register
US_BRGR # 4 ;- Baud Rate Generator Register
US_RTOR # 4 ;- Receiver Time-out Register
US_TTGR # 4 ;- Transmitter Time-guard Register
# 4 ;- Reserved
US_RPR # 4 ;- Receive Pointer Register
US_RCR # 4 ;- Receive Counter Register
US_TPR # 4 ;- Transmit Pointer Register
US_TCR # 4 ;- Transmit Counter Register
;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (USART) Reset Receiver
AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (USART) Reset Transmitter
AT91C_US_RXEN EQU (0x1:SHL:4) ;- (USART) Receiver Enable
AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (USART) Receiver Disable
AT91C_US_TXEN EQU (0x1:SHL:6) ;- (USART) Transmitter Enable
AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (USART) Transmitter Disable
AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (USART) Reset Status Bits
AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break
AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break
AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out
AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address
;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock
AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1
AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)
AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK)
AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits
AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits
AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits
AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits
AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select
AT91C_US_PAR EQU (0x7:SHL:9) ;- (USART) Parity type
AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (USART) Even Parity
AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (USART) Odd Parity
AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (USART) Parity forced to 0 (Space)
AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (USART) Parity forced to 1 (Mark)
AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (USART) No Parity
AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (USART) Multi-drop mode
AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits
AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit
AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits
AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (USART) Channel Mode
AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (USART) Normal Mode: The USART channel operates as an RX/TX USART.
AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.
AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (USART) Remote Loopback: RXD pin is internally connected to TXD pin.
AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length
AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select
;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (USART) RXRDY Interrupt
AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (USART) TXRDY Interrupt
AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break
AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (USART) End of Receive Transfer Interrupt
AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (USART) End of Transmit Interrupt
AT91C_US_OVRE EQU (0x1:SHL:5) ;- (USART) Overrun Interrupt
AT91C_US_FRAME EQU (0x1:SHL:6) ;- (USART) Framing Error Interrupt
AT91C_US_PARE EQU (0x1:SHL:7) ;- (USART) Parity Error Interrupt
AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out
AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (USART) TXEMPTY Interrupt
;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Special Function Interface
;- *****************************************************************************
^ 0 ;- AT91S_SF
SF_CIDR # 4 ;- Chip ID Register
SF_EXID # 4 ;- Chip ID Extension Register
SF_RSR # 4 ;- Reset Status Register
SF_MMR # 4 ;- Memory Mode Register
# 8 ;- Reserved
SF_PMR # 4 ;- Protect Mode Register
;- -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register --------
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