📄 lowinit.c
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/****************************************************************
** *
** FILE : LOWINIT.H *
** COPYRIGHT : (c) 2004 .Xiamen Yaxon NetWork CO.LTD *
** *
** *
** 2004/10/21 *
****************************************************************/
#include "includes.h"
#include "bsp.h"
// The following functions must be write in ARM mode this function called directly
// by exception vector
void vec_reset_handler (void)
{
SendFromUART_STR(USART1,(INT8U*) ("1EXC: Soft Reset!!\r\n"));
}
void vec_undef_handler (void)
{
SendFromUART_STR(USART1,(INT8U*)("2EXC: Undef!!\r\n"));
}
void vec_swi_handler (void)
{
SendFromUART_STR(USART1, (INT8U*) ("3EXC: SWI!!\r\n"));
}
void vec_prefetchabort_handler (INT32U addr)
{
PrintFromUART(USART1,(char*) ("4EXC: Prefetch Abort!!\r\n"));
//PrintFromUART(USART1,"\naddress=");
SendFromUART_HEX(USART1,(INT32U)addr >>24);
SendFromUART_HEX(USART1,(INT32U)addr>>16);
SendFromUART_HEX(USART1,(INT32U)addr>>8);
SendFromUART_HEX(USART1,(INT32U)addr);
}
void vec_dataabort_handler (void)
{
PrintFromUART(USART1,(char*) ("5EXC: Data Abort!!\r\n"));
//PrintFromUART(USART1,"\naddress=");
//SendFromUART_HEX(USART1,(INT32U)vecptr>>24);
//SendFromUART_HEX(USART1,(INT32U)vecptr>>16);
//SendFromUART_HEX(USART1,(INT32U)vecptr>>8);
//SendFromUART_HEX(USART1,(INT32U)vecptr);
}
void AT91F_Spurious_handler (void)
{
SendFromUART_STR(USART1,(INT8U*) ("NOTE: Entering Spurious!!\r\n"));
}
void AT91F_Default_IRQ_handler(void)
{
PrintFromUART(USART1,(char*) ("enter start IRQ interrupt!!\r\n"));
}
void AT91F_Default_FIQ_handler(void)
{
PrintFromUART(USART1,(char*) ("enter start FIQ interrupt!!\r\n"));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//* this function can be use a Stack, depending the compilation
//* optimization mode
//* Input Parameters
//* <Vector> vector table Address determinate in Relative addressing
//* <InternalRam> Internal Address determinate in Relative addressing
//* Output Parameters
//* <EBI address>
//*----------------------------------------------------------------------------
AT91_REG * AT91F_LowLevelInit( unsigned int * Vector, unsigned int * InternalRam)
{
INT32U i;
AT91PS_EBI pEbi;
AT91PS_AIC pAic;
//-----------------------------------------------------------------------------
// Speed up the Boot sequence
//---------------------------
// After reset, the number of wait states on chip select 0 is 8. All AT91
// Evaluation Boards fits fast flash memories, so that the number of wait
// states can be optimized to fast up the boot sequence.
//-----------------------------------------------------------------------------
// set sandart Wait State
pEbi = AT91C_BASE_EBI ;
pEbi->EBI_CSR[0] = EBI_CSR_0 ;
//-----------------------------------------------------------------------------
// Set up EBI value
//--------------------
// After reset, All EBI register are setted at the default value
// The new value will be effective only after the remap command
//-----------------------------------------------------------------------------
// Load System pEbi Base address and CSR0 Init Value
pEbi->EBI_CSR[1] = EBI_CSR_1 ;
pEbi->EBI_CSR[2] = EBI_CSR_2 ;
pEbi->EBI_CSR[3] = EBI_CSR_3 ;
pEbi->EBI_CSR[4] = EBI_CSR_4 ;
pEbi->EBI_CSR[5] = EBI_CSR_5 ;
pEbi->EBI_CSR[6] = EBI_CSR_6 ;
pEbi->EBI_CSR[7] = EBI_CSR_7 ;
// 6 memory regions, standard read
pEbi->EBI_MCR = AT91C_EBI_ALE_2M;
//-----------------------------------------------------------------------------
// Reset the Interrupt Controller
//-------------------------------
// Normally, the code is executed only if a reset has been actually performed.
// So, the AIC initialization resumes at setting up the default vectors.
//-----------------------------------------------------------------------------
// Load System pAic Base address
pAic = AT91C_BASE_AIC;
// Mask All interrupt
pAic->AIC_IDCR = 0xFFFFFFFF;
// Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ
for (i=0;i < 8; i++)
{
AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
}
// Set up the default interrupts handler vectors
pAic->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
for (i=1;i < 31; i++)
{
pAic->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
}
pAic->AIC_SPU = (int) AT91F_Spurious_handler ;
//-----------------------------------------------------------------------------
// Setup Exception Vectors in Internal RAM before Remap
//-----------------------------------------------------
// That's important to perform this operation before Remap in order to guarantee
// that the core has valid vectors at any time during the remap operation.
// Note: There are only 5 offsets as the vectoring is used.
// Before Remap the internal RAM it's 0x300000
// After Remap the internal RAM it's 0x000000
// Remap it's already executed it's no possible to write to 0x300000.
//-----------------------------------------------------------------------------
// Copy the ARM exception vectors and indirect table
for (i=0;i < (8+5); i++ )
{
*InternalRam++=*Vector++;
}
return ( &pEbi->EBI_RCR);
}
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