cs8900.h

在s3c2410下移植的LWIP 1.11 协议栈

/******************************************************************************
 *
 * System On Chip(SOC)
 *
 * Copyright (c) 2002 Software Center, Samsung Electronics, Inc.
 * All rights reserved.
 *
 * This software is the confidential and proprietary information of Samsung 
 * Electronics, Inc("Confidential Information"). You Shall not disclose such 
 * Confidential Information and shall use it only in accordance with the terms 
 * of the license agreement you entered into Samsung.
 *
 *-----------------------------------------------------------------------------
 *
 *	S3C2410 BSP
 *
 * cs8900dbg.h : EBOOT CS8900 ETHDBG Driver Header
 *
 * @author		[e-mail] (SOC, SWC, SAMSUNG Electronics)
 *
 * @date		2002/04/09
 * 
 * Log:
 *		2002/04/09	Start
 *      
 ******************************************************************************
 */
    
#ifndef __CS8900DBG_H__
#define __CS8900DBG_H__
#include "err.h"
/*
 * Bus interface registers
 */
#define USHORT   U16

#define PKTPG_EISA_NUMBER           0x0000
#define PKTPG_PRDCT_ID_CODE         0x0002
#define PKTPG_IO_BASE_ADDR          0x0020
#define PKTPG_INTERRUPT_NUMBER      0x0022
#define PKTPG_DMA_CHANNEL_NUMBER    0x0024
#define PKTPG_DMA_START_OF_FRAME    0x0026
#define PKTPG_DMA_FRAME_COUNT       0x0028
#define PKTPG_RX_DMA_BYTE_COUNT     0x002a
#define PKTPG_MEMORY_BASE_ADDR      0x002c
#define PKTPG_BOOT_PROM_BASE_ADDR   0x0030
#define PKTPG_BOOT_PROM_ADDR_MASK   0x0034
#define PKTPG_EEPROM_COMMAND        0x0040
#define PKTPG_EEPROM_DATA           0x0042
#define PKTPG_RX_FRAME_BYTE_COUNT   0x0050

/*
 * Status and control registers
 */
#define PKTPG_ISQ                   0x0120
#define PKTPG_RX_CFG                0x0102
#define PKTPG_RX_EVENT              0x0124
#define PKTPG_RX_CTL                0x0104
#define PKTPG_TX_CFG                0x0106
#define PKTPG_TX_EVENT              0x0128
#define PKTPG_TX_CMD_ST             0x0108
#define PKTPG_BUF_CFG               0x010a
#define PKTPG_BUF_EVENT             0x012c
#define PKTPG_RX_MISS               0x0130
#define PKTPG_TX_COL                0x0132
#define PKTPG_LINE_CTL              0x0112
#define PKTPG_LINE_ST               0x0134
#define PKTPG_SELF_CTL              0x0114
#define PKTPG_SELF_ST               0x0136
#define PKTPG_BUS_CTL               0x0116
#define PKTPG_BUS_ST                0x0138
#define PKTPG_TEST_CTL              0x0118
#define PKTPG_AUI_TIME_DOMAIN_REF   0x013c

/*
 * Initiate transmit registers
 */
#define PKTPG_TX_CMD_REQ            0x0144
#define PKTPG_TX_LENGTH             0x0146

/*
 * Address filter registers
 */
#define PKTPG_LOGICAL_ADDR_FILTER   0x0150
#define PKTPG_INDIVISUAL_ADDR       0x0158

/*
 * Frame locations
 */
#define PKTPG_RX_STATUS             0x0400
#define PKTPG_RX_LENGTH             0x0402
#define PKTPG_RX_FRAME              0x0404
#define PKTPG_TX_FRAME              0x0a00

/*
 * Bit masks
 */
#define SELF_CTL_RESET              0x0040
#define SELF_CTL_LOW_BITS           0x0015

#define SELF_ST_INITD               0x0080
#define SELF_ST_SIBUSY              0x0100

#define BUS_ST_TX_BID_ERR           0x0080
#define BUS_ST_RDY_4_TX_NOW         0x0100

#define BUS_CTL_MEMORY_E            0x0400
#define BUS_CTL_ENABLE_IRQ          0x8000
#define BUS_CTL_IOCHRDYE            0x1000
#define BUS_CTL_LOW_BITS            0x0017

#define TX_CMD_START_5              0x0000
#define TX_CMD_START_381            0x0040
#define TX_CMD_START_1021           0x0080
#define TX_CMD_START_ALL            0x00c0
#define TX_CMD_FORCE                0x0100
#define TX_CMD_ONECOLL              0x0200
#define TX_CMD_NO_CRC               0x1000
#define TX_CMD_NO_PAD               0x2000
#define TX_CMD_LOW_BITS             0x0009

#define ISQ_REG_NUM                 0x003f
#define ISQ_REG_CONTENT             0xffc0

#define RX_EVENT_RX_OK              0x0100
#define RX_EVENT_HASHED             0x0200
#define RX_EVENT_IND_ADDR           0x0400
#define RX_EVENT_BROADCAST          0x0800

#define RX_CTL_RX_OK_A              0x0100
#define RX_CTL_IND_ADDR_A           0x0400
#define RX_CTL_BROADCAST_A          0x0800
#define RX_CTL_LOW_BITS             0x0005

#define RX_CFG_SKIP                 0x0040
#define RX_CFG_RX_OK_I_E            0x0100
#define RX_CFG_LOW_BITS             0x0003

#define BUF_EVENT_RDY_4_TX          0x0100

#define BUF_CFG_RDY_4_TX_I_E        0x0100
#define BUF_CFG_LOW_BITS            0x000b

#define TX_CFG_LOSS_OF_CRC_I_E      0x0040
#define TX_CFG_SQE_ERROR_I_E        0x0080
#define TX_CFG_TX_OK_I_E            0x0100
#define TX_CFG_OUT_OF_WINDOW_I_E    0x0200
#define TX_CFG_JABBER_I_E           0x0400
#define TX_CFG_ANYCOLL_I_E          0x0800
#define TX_CFG_16_COLL_I_E          0x8000
#define TX_CFG_ALL                  0x8fc0
#define TX_CFG_LOW_BITS             0x0007

#define TX_EVENT_LOSS_OF_CRS        0x0040
#define TX_EVENT_SQE_ERROR          0x0080
#define TX_EVENT_TX_OK              0x0100
#define TX_EVENT_OUT_OF_WINDOW      0x0200
#define TX_EVENT_JABBER             0x0400
#define TX_EVENT_NUM_TX_COLL        0x7800
#define TX_EVENT_16_COLL            0x8000

/* One of the values of 0, 1, 2, 3 */
#define INTERRUPT_NUMBER            0x0000

#define LINE_CTL_10_BASE_T          0x0000
#define LINE_CTL_AUI_ONLY           0x0100
#define LINE_CTL_RX_ON              0x0040
#define LINE_CTL_TX_ON              0x0080
#define LINE_CTL_MOD_BACKOFF        0x0800
#define LINE_CTL_LOW_BITS           0x0013

#define LINE_ST_LINK_OK             0x0080
#define LINE_ST_AUI                 0x0100
#define LINE_ST_10BT                0x0200
#define LINE_ST_POLARITY_OK         0x1000
#define LINE_ST_CRS                 0x4000

#define TEST_CTL_FDX                0x4000
#define TEST_CTL_LOW_BITS           0x0019

/*
 * Register numbers
 */
#define REG_NUM_RX_EVENT            0x0004
#define REG_NUM_TX_EVENT            0x0008
#define REG_NUM_BUF_EVENT           0x000c
#define REG_NUM_RX_MISS             0x0010
#define REG_NUM_TX_COL              0x0012

#define	IO_ADDR_SFT					0
/*
 * I/O mode register mapping
 */
#define IO_RX_TX_DATA_0             (0x0000<<IO_ADDR_SFT)
#define IO_RX_TX_DATA_1             (0x0002<<IO_ADDR_SFT)
#define IO_TX_CMD                   (0x0004<<IO_ADDR_SFT)
#define IO_TX_LENGTH                (0x0006<<IO_ADDR_SFT)
#define IO_ISQ                      (0x0008<<IO_ADDR_SFT)
#define IO_PACKET_PAGE_POINTER      (0x000a<<IO_ADDR_SFT)
#define IO_PACKET_PAGE_DATA_0       (0x000c<<IO_ADDR_SFT)
#define IO_PACKET_PAGE_DATA_1       (0x000e<<IO_ADDR_SFT)


		/* CS8900 signature read from PacketPage Pointer port at reset	*/
#define CS8900_SIGNATURE			0x3000
#define	CS8900_SIGMSK				0x3000
#define CS8900_EISA_NUMBER			0x630e		/* CS8900 EISA number	*/
#define CS8900_PRDCT_ID				0x0000		/* CS8900 product ID	*/
#define CS8900_PRDCT_ID_MASK		0xe0ff

typedef unsigned char                   byte;
typedef unsigned short                  word;
typedef unsigned long int               dword;

//#define SMC_DEBUG 3
/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */

#define SMC_IO_EXTENT   16


/*---------------------------------------------------------------
 .  
 . A description of the SMSC registers is probably in order here,
 . although for details, the SMC datasheet is invaluable.  
 . 
 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
 . are accessed by writing a number into the BANK_SELECT register
 . ( I also use a SMC_SELECT_BANK macro for this ).
 . 
 . The banks are configured so that for most purposes, bank 2 is all
 . that is needed for simple run time tasks.  
 -----------------------------------------------------------------------*/

/*
 . Bank Select Register: 
 .
 .              yyyy yyyy 0000 00xx  
 .              xx              = bank number
 .              yyyy yyyy       = 0x33, for identification purposes.
*/
#define BANK_SELECT             14

// Transmit Control Register
/* BANK 0  */
#define TCR_REG         0x0000  // transmit control register 
#define TCR_ENABLE      0x0001  // When 1 we can transmit
#define TCR_LOOP        0x0002  // Controls output pin LBK
#define TCR_FORCOL      0x0004  // When 1 will force a collision
#define TCR_PAD_EN      0x0080  // When 1 will pad tx frames < 64 bytes w/0
#define TCR_NOCRC       0x0100  // When 1 will not append CRC to tx frames
#define TCR_MON_CSN     0x0400  // When 1 tx monitors carrier
#define TCR_FDUPLX      0x0800  // When 1 enables full duplex operation
#define TCR_STP_SQET    0x1000  // When 1 stops tx if Signal Quality Error
#define TCR_EPH_LOOP    0x2000  // When 1 enables EPH block loopback
#define TCR_SWFDUP      0x8000  // When 1 enables Switched Full Duplex mode

#define TCR_CLEAR       0       /* do NOTHING */
/* the default settings for the TCR register : */ 
/* QUESTION: do I want to enable padding of short packets ? */
#define TCR_DEFAULT     TCR_ENABLE 


// EPH Status Register
/* BANK 0  */
#define EPH_STATUS_REG  0x0002
#define ES_TX_SUC       0x0001  // Last TX was successful
#define ES_SNGL_COL     0x0002  // Single collision detected for last tx
#define ES_MUL_COL      0x0004  // Multiple collisions detected for last tx
#define ES_LTX_MULT     0x0008  // Last tx was a multicast
#define ES_16COL        0x0010  // 16 Collisions Reached
#define ES_SQET         0x0020  // Signal Quality Error Test
#define ES_LTXBRD       0x0040  // Last tx was a broadcast
#define ES_TXDEFR       0x0080  // Transmit Deferred
#define ES_LATCOL       0x0200  // Late collision detected on last tx
#define ES_LOSTCARR     0x0400  // Lost Carrier Sense
#define ES_EXC_DEF      0x0800  // Excessive Deferral
#define ES_CTR_ROL      0x1000  // Counter Roll Over indication
#define ES_LINK_OK      0x4000  // Driven by inverted value of nLNK pin
#define ES_TXUNRN       0x8000  // Tx Underrun


// Receive Control Register
/* BANK 0  */
#define RCR_REG         0x0004
#define RCR_RX_ABORT    0x0001  // Set if a rx frame was aborted
#define RCR_PRMS        0x0002  // Enable promiscuous mode
#define RCR_ALMUL       0x0004  // When set accepts all multicast frames
#define RCR_RXEN        0x0100  // IFF this is set, we can receive packets
#define RCR_STRIP_CRC   0x0200  // When set strips CRC from rx packets
#define RCR_ABORT_ENB   0x0200  // When set will abort rx on collision 
#define RCR_FILT_CAR    0x0400  // When set filters leading 12 bit s of carrier
#define RCR_SOFTRST     0x8000  // resets the chip

/* the normal settings for the RCR register : */
#define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN|RCR_PRMS)
//#define RCR_DEFAULT     0xFFFF
#define RCR_CLEAR       0x0     // set it to a base state

// Counter Register
/* BANK 0  */
#define COUNTER_REG     0x0006

// Memory Information Register
/* BANK 0  */
#define MIR_REG         0x0008

// Receive/Phy Control Register
/* BANK 0  */
#define RPC_REG         0x000A
#define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
#define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
#define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
#define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
#define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb