📄 cp.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY cp is
PORT(
clk:IN std_logic;
cp1:OUT std_logic;
cp2:OUT std_logic
);
END;
ARCHITECTURE freq of cp IS
SIGNAL count:std_logic_vector(19 downto 1);
SIGNAL c1:std_logic;
SIGNAL c2:std_logic;
BEGIN
PROCESS(clk)
BEGIN
IF(clk'event and clk='1')then
IF(count="1111010000100011111")then
count<="0000000000000000000";
c1<=not c1;
ELSE count<=count+1;
END IF;
c2<=count(10);
END IF;
END PROCESS;
cp1<=c1;cp2<=c2;
END;
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