📄 fswitch.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY fswitch IS
PORT( clk:IN std_logic;
run:IN std_logic;
mode:IN std_logic;
rp:IN std_logic;
runO:OUT std_logic;
modeO:OUT std_logic;
rpO:OUT std_logic);
END;
ARCHITECTURE impulse of fswitch IS
SIGNAL cp:std_logic_vector(3 downto 1);
SIGNAL jsq1:std_logic_vector(8 downto 0);
SIGNAL jsq2:std_logic_vector(8 downto 0);
SIGNAL jsq3:std_logic_vector(8 downto 0);
BEGIN
PROCESS(clk)
BEGIN
IF(clk'event and clk='1')THEN
IF(run='1')THEN
IF(jsq1="111111111")THEN jsq1<=jsq1;
ELSE jsq1<=jsq1+1;
END IF;
IF(jsq1="111111110")THEN cp(1)<=not cp(1);
END IF;
ELSE IF(jsq1="000000000")THEN jsq1<=jsq1;
ELSE jsq1<=jsq1-1;
END IF;
END IF;
IF(mode='1')THEN
IF(jsq2="111111111")THEN jsq2<=jsq2;
ELSE jsq2<=jsq2+1;
END IF;
IF(jsq2="100000000")THEN cp(2)<='1';
ELSE cp(2)<='0';
END IF;
ELSE IF(jsq2="000000000")THEN jsq2<=jsq2;
ELSE jsq2<=jsq2-1;
END IF;
END IF;
IF(rp='1')THEN
IF(jsq3="111111111")THEN jsq3<=jsq3;
ELSE jsq3<=jsq3+1;
END IF;
IF(jsq3="100000000")THEN cp(3)<='1';
ELSE cp(3)<='0';
END IF;
ELSE IF(jsq3="000000000")THEN jsq3<=jsq3;
ELSE jsq3<=jsq3-1;
END IF;
END IF;
END IF;
END PROCESS;
runO<=cp(1);
modeO<=cp(2);
rpO<=cp(3);
END;
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