📄 fset.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY fset IS
PORT(
run:IN std_logic;
mode:IN std_logic;
reset:IN std_logic;
status:OUT std_logic_vector(2 downto 0)
);
END;
--------------------------------------------------------
ARCHITECTURE pro of fset IS
SIGNAL s:std_logic_vector(2 downto 0);
BEGIN
PROCESS(mode)
BEGIN
IF(reset='1')THEN
status<="001";
ELSE IF(mode'event and mode='1')THEN
IF(run='0')THEN
IF(s="100")THEN
s<="000";
ELSE
s<=s+1;
END IF;
status(2)<=((not s(0))and s(1))or s(2); ----wash
status(1)<=s(0)or s(2); ------clean
status(0)<=not(s(0)xor s(1))or s(2); -----dry
END IF;
END IF;
END IF;
END PROCESS;
END;
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