nios.prjpcbstructure

nios ii 开发板原理图

Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=04_CPU_POWER.SchDoc
Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=10_LCD_LED_KEY.SchDoc
Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=07_SRAM.SCHDOC
Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=03_CPU.SchDoc
Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=09_SDRAM.SCHDOC
Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=06_I_O_EXT.SchDoc
Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=02_JTAG_AS.SchDoc
Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=08_FLASH.SchDoc
Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=01_POWER.SchDoc
Record=SheetSymbol|SourceDocument=MAIN.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=05_CLK_RST_XTAL.SchDoc
Record=TopLevelDocument|FileName=MAIN.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=U1|DocumentName=03_CPU.SchDoc|LibraryReference=EP1C12Q240C8|SubProjectPath= |Configuration= |Description=Cyclone Family, 1.5V FPGA, 173 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 8|SubPartUniqueId1=FCMAYVWY|SubPartDocPath1=03_CPU.SchDoc|SubPartUniqueId2=XEPREPOB|SubPartDocPath2=02_JTAG_AS.SchDoc|SubPartUniqueId3=RUUAVYNF|SubPartDocPath3=04_CPU_POWER.SchDoc|SubPartUniqueId4=BJOVWRTH|SubPartDocPath4=05_CLK_RST_XTAL.SchDoc