nios ii.drc

nios ii 开发板原理图

Protel Design System Design Rule Check
PCB File : \Red Cyclone Mainboard\NIOS\NIOS II.PcbDoc
Date     : 2008-5-11
Time     : 9:36:13

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
   Violation         Pad J1_1-3(1195.198mil,4493.228mil)  Multi-Layer  Actual Hole Size = 110.236mil
   Violation         Pad J1_1-2(1341.198mil,4316.228mil)  Multi-Layer  Actual Hole Size = 110.236mil
   Violation         Pad J1_1-1(1066.198mil,4316.228mil)  Multi-Layer  Actual Hole Size = 110.236mil
Rule Violations :3

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=7mil) (Max=20mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=7mil) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0


Violations Detected : 3
Time Elapsed        : 00:00:00