config.h

WindML BSP specific routines

/* mbx860/config.h - Motorola MBX860/821 board configuration header */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1997,1999 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
02b,12jun02,kab  SPR 74987: cplusplus protection
02a,17may02,dtr  Changing INCLUDE_AUXCLK to INCLUDE_AUX_CLK.
01z,07may02,dtr  Undefining LOCAL_MEM_AUTOSIZE. See SPR 31148.
01y,05apr02,dtr  Adding TFFS support for PCMCIA Flash cards also reducing 
                 PCI_MSTR_IO_SIZE,PCI_MSTR_IO_CODE to reduce MMU memory usage.
01x,07mar02,dtr  Adding Auxilliary clock as a configurable item although left
                 undefined.
01w,30jan02,dtr  Changing definition name ATA_DEV_NONE to NO_ATA_DEV. 
                 Conflicted with ataDrv.h define.
01v,30oct01,dtr  Including fix to SPR65678. This creates a define USE_KEYED_REG
                 which includes fix for board lockup with backup battery
                 connected.
01u,10mar00,rcs  mere mot's latest version
01t,30nov99,rhk  added defines for selecting UPM tables for 50MHz boards,
		 and ISA edge/level sensitive interrupt selection.
01s,11mar99,dat  merged with mot's latest version
01r,10jul98,sut  changed BSP_VERSION to "1.2" and BSP_REV to "/0"
                 added BSP_VER_1_2 macro ( Tornado 2.0 release ).
01q,22jun98,cn   added support for Enhanced Network Driver.
01p,06may98,rhk  added PTE macros, explanations for setting up PCI space
                 added PCI_MSTR, PCI_SLV macros, moved non-configurable
		 macros to mbx800.h
01o,07apr98,dat  QSPAN macro changes
01n,26mar98,map  code cleanup
            rhk  added QSPAN macros
01m,11mar98,rhk  removed keyboard/LCD configuration defines.
01l,10mar98,rhk  WRS code review cleanup.
01k,20jan98,srr  updated for release 0.8 to fix pciDeviceShow and UMPA table.
01j,18nov97,rhk  WRS code review cleanup.
01i,17nov97,srr  updated for release 0.7 to add i2c microcode patch and fix
		 vxWorks.st_rom problem.
01h,14nov97,srr  change the ROM_SIZE to 512K.
01g,24oct97,srr  updated for release 0.6 to modify UMPA tables in romInit.
01f,04sep97,scb  updated for keyboard integration.
01e,25aug97,srr  updated for release 0.4 to remove pci.h and fix sysMsDelay.
01d,05aug97,srr  updated for release 0.3 and removed STANDALONE setup.
01c,10jul97,rhk	 added configuration constants for ATA driver
01b,08jul97,srr  updated for release 0.2.
01a,26jun97,srr  created from ads860.
*/

/*
This file contains the configuration parameters for the Motorola MBX860/821
boards.
*/

#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
    extern "C" {
#endif

/* 
 * BSP version/revision identification, should be placed
 * before #include "configAll.h"
 */

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "1.2"
#define BSP_REV         "/1"		/* 0 for the first bsp revision */

#include "configAll.h"

#define DEFAULT_BOOT_LINE \
"cpm(0,0)host:/tor/target/config/mbx860/vxWorks h=90.0.0.3 e=90.0.0.50 u=target"

/*
 * Note: For configuring the kernel based on board Revision, the
 * following defines should be set appropriately.
 *
 * If using a Rev. C or later board, define USER_D_CACHE_ENABLE.  This
 * will greatly increase performance.
 * 
 * If using a pre-Rev. C board define ISA_DUAL_MODE_INTRS.  This will
 * support both level and edge sensitive interrupts for the ISA
 * interrupt controller.  The advantage of this is that it will
 * allow interrupt sharing for PCI/ISA interrupts.
 *
 * A list of marketing and Assembly numbers for each revision of MBX
 * boards is in target.nr.
 */

#undef USER_D_CACHE_ENABLE	/* disable cache for pre-Rev C boards */
#undef ISA_DUAL_MODE_INTRS     /* Rev C supports only edge triggered intrs */

/*
 * For 50MHz boards, two UPMA tables exist, a "fast" version which is
 * the officially supported UPMA table for 50MHz, and an "enhanced"
 * version which provides a slight performance speedup over the "fast"
 * version, but is not officially supported.  The fast version is 
 * selected by default.  To use the enhanced table, define ENHANCED_UPMA,
 * rebuild and reflash the bootrom.
 */

#undef ENHANCED_UPMA		/* define to use the enhanced table values */

#define INCLUDE_END             /* Enhanced Network Driver see configNet.h */
 
/* Define board type -- BOARD_TYPE_ENTRY or BOARD_TYPE_STANDARD */

#define BOARD_TYPE		BOARD_TYPE_ENTRY

/* Define serial port - SERIAL_PORT_SMC or SERIAL_PORT_COM */

#define SERIAL_PORT 		SERIAL_PORT_SMC

/* Cache and MMU supported */

#define USER_I_MMU_ENABLE
#define USER_D_MMU_ENABLE
#define INCLUDE_MMU_BASIC

/* USE_KEYED_REGS significantly reduces the boot lockup problem when backup \
   battery attached (h/w errata). It also increases the amount of time spent 
   in the timer interrupt handler. If defined, you should create a new 
   bootrom and be aware that both the bootrom and the vxWorks image must both
   have this define for the fix to be effective. 
*/
#undef USE_KEYED_REGS 

/* if running image where exception vector table is more than 24 bit 
   adressing away from handler this will be required. Not required 
   for standard BSP.*/ 

#undef INCLUDE_EXC_EXTENDED_VECTOR

#ifdef INCLUDE_EXC_EXTENDED_VECTOR
#define INCLUDE_SYS_HW_INIT_0
#endif /*INCLUDE_EXC_EXTENDED_VECTOR */

#ifdef INCLUDE_SYS_HW_INIT_0
    /*
     * Perform any BSP-specific initialisation that must be done before
     * cacheLibInit() is called and/or BSS is cleared.
     */

#ifndef _ASMLANGUAGE
IMPORT BOOL excExtendedVectors; 
extern void sysHwInit0();
#endif /*_ASMLANGUAGE */

#define SYS_HW_INIT_0 sysHwInit0
#endif /* INCLUDE_SYS_HW_INIT_0 */

/* add necessary drivers */

#define INCLUDE_PCI			/* include the PCI library support */
#define INCLUDE_CPM_END			/* include the CPM ethernet driver */

/* Optional Drivers */

#undef  INCLUDE_TIMESTAMP		/* Optional timestamp support */
#undef  INCLUDE_AUX_CLK                  /* Optional auxilliary clock support */
#undef	INCLUDE_ATA			/* Optional EIDE driver */
#undef	INCLUDE_LPT			/* Optional Parallel Port support */
#undef	INCLUDE_MBX_PCMCIA		/* Optional PCMCIA support */
#undef	INCLUDE_DOSFS			/* Optional DOS file system support */

#ifdef	INCLUDE_ATA
#define	INCLUDE_DOSFS
#endif	/* INCLUDE_ATA */

#ifdef INCLUDE_TFFS
#define	INCLUDE_MBX_PCMCIA
#endif

#ifdef  INCLUDE_TIMESTAMP
#define INCLUDE_AUX_CLK
#endif
/* Define the Size of the PCMCIA region */

#define PCMCIA_SIZE	MEM_SIZE_64MB	/* PCMCIA region size - 64MB */

/* 
 * The ATA_DEVx_CYL defines are used by the ATA driver to determine
 * whether or not a device should be considered to be present in the
 * system.
 *
 * If ATA_DEVx_CYL is NO_ATA_DEV, the driver will not attempt to configure
 * the device, but for an existing device, the appropriate
 * ATA_DEVx_CYL should be set to ATA_DEV_EXIST. This will cause
 * the driver to automatically probe the device for its configuration
 * parameters and configure the device into the system.
 */

#define ATA_DEV0_CYL	ATA_DEV_EXIST		/* controller 0, drive 0 */
#define ATA_DEV1_CYL	NO_ATA_DEV		/* controller 0, drive 1 */
#define ATA_DEV2_CYL	NO_ATA_DEV		/* controller 1, drive 0 */
#define ATA_DEV3_CYL	NO_ATA_DEV		/* controller 1, drive 1 */


/* remove unnecessary drivers */

#undef INCLUDE_BP
#undef INCLUDE_EX
#undef INCLUDE_ENP
#undef INCLUDE_SM_NET
#undef INCLUDE_SM_SEQ_ADD

/* Memory addresses */

#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* Base of RAM */
#define LOCAL_MEM_SIZE		0x00400000	/* 4 Mbyte is the default */ 

/*
 * To have the kernel perform dynamic memory sizing, add the define for
 * LOCAL_MEM_AUTOSIZE.  
 * Warning: when building the bootrom with this define enabled,
 * it can take up to 16 seconds for the boot prompt to appear
 * after power is applied.  ( The kernel clears all unused memory )
 * LOCAL_MEM_AUTOSIZE assumes the soldered RAM and the DIMMs are contiguous
 * in memory space. If not the board will hang.See SPR 31148.
 */

#undef  LOCAL_MEM_AUTOSIZE

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, and RAM_HIGH_ADRS are defined
 * in config.h, and Makefile.
 * All definitions for these constants must be identical.
 */

#define ROM_BASE_ADRS		0xFE000000	/* base address of ROM */
#define ROM_TEXT_ADRS		(ROM_BASE_ADRS + 0x100)

#define ROM_SIZE		0x00080000 	/* 512K ROM space */

/* RAM address for ROM boot */

#define RAM_HIGH_ADRS		(LOCAL_MEM_LOCAL_ADRS + 0x00200000)

/* RAM address for sys image */

#define RAM_LOW_ADRS		(LOCAL_MEM_LOCAL_ADRS + 0x00010000)

#define USER_RESERVED_MEM	0x00000000	/* user reserved memory size */

/*
 * Select default CPU power management mode. Power management
 * modes available on PPC860 are,
 * 
 *   VX_POWER_MODE_DISABLE,  disable power management
 *   VX_POWER_MODE_FULL,  all CPU units are active
 *   VX_POWER_MODE_DOZE,  `doze'  mode
 *   VX_POWER_MODE_SLEEP,  `sleep' mode
 *   VX_POWER_MODE_DEEP_SLEEP,  `deep-sleep' mode
 *   VX_POWER_MODE_DOWN,  all units are down
 *
 * The CPU is set to DEFAULT_POWER_MGMT_MODE in sysHwInit().
 */

#define DEFAULT_POWER_MGT_MODE  VX_POWER_MODE_DISABLE

/* 
 * The following macros define access to PCI space from the CPU,
 * and access to local DRAM from the PCI bus.  
 *
 * See target.nr for descriptions of PCI Space configurations.
 *
 * NOTE: when changing address bases or size values, be careful not
 * to overlap with any other address spaces defined for the system.
 *
 * Map local access to PCI Mem Space
 *
 *   PCI_MSTR_MEM_LOCAL	- Base address for PCI Mem access
 *   PCI_MSTR_MEM_BUS	- Base address of PCI Mem space on Bus
 *   PCI_MSTR_MEM_SIZE	- Size of PCI Mem window
 *   PCI_MSTR_MEM_CODE	- Size of PCI Mem window for QSPAN setup
 *
 * Map local access to PCI I/O Space
 *
 *   PCI_MSTR_IO_LOCAL 	- Base address for PCI I/O access
 *   PCI_MSTR_IO_BUS	- Base address of PCI I/O space on Bus
 *   PCI_MSTR_IO_SIZE	- Size of PCI I/O window
 *   PCI_MSTR_IO_CODE	- Size of PCI I/O window for QSPAN setup
 *
 * Map PCI memory access to local CPU space
 *
 *   PCI_SLV_MEM_LOCAL	- Base address of Local CPU space
 *   PCI_SLV_MEM_BUS	- Base address of local memory as seen from PCI Bus
 *   PCI_SLV_MEM_SIZE	- Size of Window for Local space access
 *   PCI_SLV_MEM_CODE	- Size of Translation Address window for QSPAN
 *
 * Map PCI I/O access to local CPU space (not used)
 * 
 *   PCI_SLV_IO_LOCAL
 *   PCI_SLV_IO_BUS
 *   PCI_SLV_IO_SIZE
 *   PCI_SLV_IO_CODE
 *
 * Base address of PCI I/O space as seen by CPU, also used for 
 * calculating the base of PCI Mem space,
 *
 *   (PCI_MSTR_MEM_LOCAL = PCI_MSTR_IO_LOCAL + 0x40000000).
 */

#define PCI_MSTR_IO_LOCAL	0x80000000	/* Set by BR5/CR5 */
#define PCI_MSTR_MEM_LOCAL	(PCI_MSTR_IO_LOCAL + 0x40000000)

/*
 * PCI_MSTR_IO_SIZE is used for setting the window sizes of both PCI I/O
 * space and PCI Mem space when setting up the Chip Select registers.
 *
 * Only one chip select register is available for PCI space, so I/O space and
 * Mem space must be the same.  PCI_MSTR_MEM_SIZE is automatically set to the
 * value defined here.  Minimum size is 64 KB, maximum size is 512MB.
 */

#define PCI_MSTR_IO_SIZE	MEM_SIZE_8MB	/* defaults to 8MB size */
#define PCI_MSTR_MEM_SIZE	PCI_MSTR_IO_SIZE

/*
 * The macro PCI_MSTR_IO_CODE defines the window size that the QSPAN chip
 * opens for PCI I/O space onto the PCI Bus -- the QSPAN SLAVE Translation
 * address size).
 * 
 * The size can range up to the size specified for PCI_MSTR_IO_SIZE, but
 * ideally should be set to the same value.  Setting it a smaller value will
 * limit the amount of PCI I/O space available.
 * 
 * The macro PCI_MSTR_MEM_CODE defines the window size that the QSPAN chip
 * opens for PCI Mem space onto the PCI Bus -- the QSPAN SLAVE Translation
 * address size.
 *
 * This define requires a coded value (QSPAN_QBSI_xxxx) from qspanPci.h.
 */

#define PCI_MSTR_IO_CODE	QSPAN_QBSI_8MB 	/* default = 8MB */
#define PCI_MSTR_MEM_CODE	PCI_MSTR_IO_CODE

/* 
 * This macro defines the base of PCI Mem on the PCI bus.  This is the
 * address that the QSPAN will translate the PCI_MSTR_IO_LOCAL value to
 * 
 * This value must be 0 if adding ISA devices in MEM space.
 */

#define PCI_MSTR_MEM_BUS	0x00000000

/*
 * The macro PCI_SLV_MEM_BUS sets the base value for PCI Mem space access of
 * local memory.  A PCI memory device that puts this address onto the bus will
 * access local memory at the address specified by PCI_SLV_MEM_LOCAL
 */

#define PCI_SLV_MEM_BUS		0x80000000

/* 
 * The macro PCI_SLV_MEM_LOCAL is the local memory address which is mapped
 * into PCI space.
 */ 

#define PCI_SLV_MEM_LOCAL	LOCAL_MEM_LOCAL_ADRS

/*
 * The macro PCI_SLV_MEM_SIZE and PCI_SLV_MEM_CODE specify the range of Local
 * memory space as it appears on the PCI bus.
 */

#define PCI_SLV_MEM_SIZE	0x80000000	/* max is 2GB */
#define PCI_SLV_MEM_CODE	QSPAN_QBTI_2GB	/* for setting the QSPAN */
						/* Translation Address size */
						/* use the QBTI_ size codes */

#include "mbx800.h"				/* include mbx8xx params */

#ifdef __cplusplus
    }
#endif

#endif	/* INCconfigh */
#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif