📄 mbxi2c.c
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if ((value > 60)) counter++; if (counter) return ((UINT)-2); /* return the size of this DRAM array */ counter = *(pBuf + 3) & 0x7F; /* rows */ counter += *(pBuf + 4); /* columns */ value = (1 << counter); counter = *(pBuf + 6) / 32; /* width */ value *= counter; value *= 4; /* 4-bytes/32 */ return (value); }/******************************************************************************** mbxI2cSromRead - read SROM for DRAM information* * This function's purpose is to retrieve the serial presence* detect data (the first 16 bytes) from the specified EEPROM.* These EEPROMs are located on the I2C bus.** RETURNS: size of DRAM array in bytes if OK or* -1 if I2C device access error, -2 if data failed sanity check*/LOCAL UINT mbxI2cSromRead ( FAST UINT i2cDevAdrs, /* I2C device address */ FAST UCHAR *pBuf, /* buffer pointer (>= 16 bytes) */ FAST UINT devOffset, /* I2C address offset */ FAST UINT byteCount /* I2C bytes to read */ ) { FAST UINT counter; /* counter variable */ FAST UINT inc; /* increment size variable */ I2C_CMD_PKT i2cp; /* command packet */ /* reset eeprom internal address index */ i2cp.csword = (I2C_IO_C_WDATA); i2cp.devAdrs = i2cDevAdrs; i2cp.dataAdrs = (UINT)pBuf; i2cp.dataSize = 1; *pBuf = devOffset; /* start from desired offset */ /* call the MPC8xx I2C bus device driver, exit on error */ mbxI2cdMain(&i2cp); if (i2cp.csword & I2C_IO_S_ERROR) return ((UINT)-1); if (byteCount % 4) inc = 1; /* not evenly divisible by 4. */ else inc = 4; /* evenly divisible by 4. */ for (counter = 0; counter < byteCount; counter += inc) { /* read "inc" bytes from the device */ i2cp.csword = (I2C_IO_C_RDATA); i2cp.devAdrs = i2cDevAdrs; i2cp.dataAdrs = (UINT)(pBuf + counter); i2cp.dataSize = inc; /* call the MPC8xx I2C bus device driver, exit on error */ mbxI2cdMain(&i2cp); if (i2cp.csword & I2C_IO_S_ERROR) return ((UINT)-1); } return (0); }/******************************************************************************** mbxI2cSromValueGet - read a particular value from SROM* * This function's purpose find and read a particular value* from the SROM buffer. The field read is associated with* the input parameters describing field ID and field size. * * RETURNS: OK or ERROR if did not find data*/LOCAL int mbxI2cSromValueGet ( FAST UINT fieldId, FAST UINT fieldSize, FAST UCHAR *resultsPtr ) { int index; int dataPtr; UINT8 dataSize; int hdr1; int hdr2; hdr1 = 0x4d4f544f; /* "MOTO" */ hdr2 = 0x524f4c41; /* "ROLA" */ /* check for "MOTOROLA" string at start of SROM buffer */ if ((hdr1 != *(int *)DPRAM_SROM_BUFFER) || (hdr2 != *(int *)(DPRAM_SROM_BUFFER+4)) ) return (ERROR); dataPtr = 0; dataSize = 0; index = 0x0a; /* set index to start of actual data fields */ /* loop until end of valid SROM data is hit or data field is found */ while (index != 0xff) { /* * check for identifier match, and that data size is not * 0 or 0xff */ dataSize = *(UCHAR *)(DPRAM_SROM_BUFFER + index + 1); if (*(UCHAR *)(DPRAM_SROM_BUFFER + index) == fieldId ) { if ((dataSize != 0) && (dataSize != 0xff)) { /* found the data, exit the loop */ dataPtr = index + 2; break; } else { return (ERROR); } } else { index = index + dataSize + 2; } } if (dataPtr == 0) return (ERROR); /* did not find the requested data */ /* copy the requested data */ for (index = 0; index < fieldSize; index++) *resultsPtr++ = *((UCHAR *)(DPRAM_SROM_BUFFER + dataPtr++)); return (OK); }/********************************************************************************* mbxI2cConfigParamsGet - get the board configuration parameters out of SROM** This routine will read board specific parameters via the I2C from the* SROM and the DIMM. The results will be store in temprory variables in* DPRAM, and then copied into global variables in sysHwInit.** RETURNS: N/A*/void mbxI2cConfigParamsGet(void) { UINT32 buffer[(SROM_MAX_ITEM_SIZE+3)/4]; UINT32 memSize; UINT32 brValue; UCHAR *dataPtr; int status; UINT immrVal = INTERNAL_MEM_MAP_ADDR; /* Base address of Internal Memory */ dataPtr = (UCHAR *)DPRAM_SROM_BUFFER; status = (int)mbxI2cSromRead (0xA4, dataPtr, 0, 256); /* read the internal clock rate */ status = mbxI2cSromValueGet (SROM_PID_ICS, SROM_SIZE_ICS, (UCHAR *)&buffer[0]); if ( status < 0 ) buffer[0] = DEFAULT_CLOCK_SPEED; switch( buffer[0] ) { case FREQ_25_MHZ: *(UINT32 *)(DPRAM_INT_CLK_SPD) = FREQ_25_MHZ; break; case FREQ_40_MHZ: *(UINT32 *)(DPRAM_INT_CLK_SPD) = FREQ_40_MHZ; break; case FREQ_50_MHZ: *(UINT32 *)(DPRAM_INT_CLK_SPD) = FREQ_50_MHZ; break; default: *(UINT32 *)(DPRAM_INT_CLK_SPD) = DEFAULT_CLOCK_SPEED; break; } /* read the external clock rate */ status = mbxI2cSromValueGet (SROM_PID_ECS, SROM_SIZE_ECS, (UCHAR *)&buffer[0]); if ( status < 0 ) buffer[0] = DEFAULT_CLOCK_SPEED; switch (buffer[0]) { case FREQ_25_MHZ: *(UINT32 *)(DPRAM_EXT_CLK_SPD) = FREQ_25_MHZ; break; case FREQ_40_MHZ: *(UINT32 *)(DPRAM_EXT_CLK_SPD) = FREQ_40_MHZ; break; case FREQ_50_MHZ: *(UINT32 *)(DPRAM_EXT_CLK_SPD) = FREQ_50_MHZ; break; default: *(UINT32 *)(DPRAM_EXT_CLK_SPD) = DEFAULT_CLOCK_SPEED; break; } /* read the size of the DIMMs */ memSize = mbxI2cEepromRead (0xa2, (UCHAR *)&buffer[0], 0); switch (memSize) { case MEM_SIZE_8MB: *(UINT32 *)(DPRAM_DIMM_SIZE) = MEM_SIZE_8MB; break; case MEM_SIZE_16MB: *(UINT32 *)(DPRAM_DIMM_SIZE) = MEM_SIZE_16MB; break; case MEM_SIZE_32MB: *(UINT32 *)(DPRAM_DIMM_SIZE) = MEM_SIZE_32MB; break; case MEM_SIZE_64MB: *(UINT32 *)(DPRAM_DIMM_SIZE) = MEM_SIZE_64MB; break; case MEM_SIZE_128MB: *(UINT32 *)(DPRAM_DIMM_SIZE) = MEM_SIZE_128MB; break; default: *(UINT32 *)(DPRAM_DIMM_SIZE) = DEFAULT_DIMM_SIZE; break; } /* read the size of the onboard DRAM */ memSize = mbxI2cEepromRead (0xa6, (UCHAR *)&buffer[0], 0); switch (memSize) { case MEM_SIZE_4MB: *(UINT32 *)(DPRAM_DRAM_SIZE) = MEM_SIZE_4MB; break; case MEM_SIZE_16MB: *(UINT32 *)(DPRAM_DRAM_SIZE) = MEM_SIZE_16MB; break; case MEM_SIZE_32MB: *(UINT32 *)(DPRAM_DRAM_SIZE) = MEM_SIZE_32MB; break; case MEM_SIZE_64MB: *(UINT32 *)(DPRAM_DRAM_SIZE) = MEM_SIZE_64MB; break; default: *(UINT32 *)(DPRAM_DRAM_SIZE) = DEFAULT_DRAM_SIZE; break; } *(UINT32 *)(DPRAM_TOTAL_RAM_SIZE) = (*(UINT32 *)(DPRAM_DRAM_SIZE) + *(UINT32 *)(DPRAM_DIMM_SIZE)); /* read the Ethernet Address for the board */ status = mbxI2cSromValueGet (SROM_PID_EA, SROM_SIZE_EA, (UCHAR *)(DPRAM_ENET_ADDR)); /* read the board device options words */ status = mbxI2cSromValueGet (SROM_PID_PCO, SROM_SIZE_PCO, (UCHAR *)&buffer[0]); if (status < 0) *(UINT32 *)(DPRAM_QSPAN_PRSNT) = FALSE; else { if (buffer[0] & PCO_PCI_DEVICE) *(UINT32 *)(DPRAM_QSPAN_PRSNT) = TRUE; else *(UINT32 *)(DPRAM_QSPAN_PRSNT) = FALSE; } /* * for the MBX product we need to determine which FLASH * memory the reset code is running from, it's either the * 8-bit wide socketed type, or the 32-bit wide soldered * type, this can be determined by examing the port-size * bit-field of the "boot" chip select base address register */ brValue = *BR0(INTERNAL_MEM_MAP_ADDR); if ((brValue & BR_PS_MSK) == BR_PS_8) *(UINT32 *)(DPRAM_BOOT_TYPE) = BOOTROM_STARTUP; else *(UINT32 *)(DPRAM_BOOT_TYPE) = FLASH_STARTUP; /* get the speed of the DRAMs, TBD - Field is not yet defined in SROM */ *(UINT32 *)(DPRAM_DRAM_SPD) = DEFAULT_MEM_SPEED; /* get the size of the FLASH mem, TBD - Field is not yet defined in SROM */ *(UINT32 *)(DPRAM_FLASH_SIZE) = DEFAULT_FLASH_SIZE; /* Set the DPRAM_REF_CLK_FRQ */ if ((*PLPRCR(immrVal) & PLPRCR_MF_MSK) == 0) *(UINT32 *)(DPRAM_REF_CLK_FRQ) = *(UINT32 *)(DPRAM_INT_CLK_SPD); else *(UINT32 *)(DPRAM_REF_CLK_FRQ) = 32768; /* 32768 Hz */ }/********************************************************************************* mbxI2cMemcConfig - configure the MEMC registers** This routine will perform the final adjustments to the Memory* Controller Bank/Option registers.** RETURNS: N/A*/void mbxI2cMemcConfig(void) { UINT32 dimmSize; UINT32 dramSize; UINT32 temp; /* get the sizes of DRAM and DIMM */ dimmSize = *(UINT32 *)(DPRAM_DIMM_SIZE); dramSize = *(UINT32 *)(DPRAM_DRAM_SIZE); /* configure the base/option registers for onboard DRAM */ temp = *OR1(INTERNAL_MEM_MAP_ADDR); *OR1(INTERNAL_MEM_MAP_ADDR) = ((~dramSize + 1) & OR_AM_MSK) | (temp & OR_OPTIONS_BITS_MSK); temp = *BR1(INTERNAL_MEM_MAP_ADDR) | BR_V; if ( dramSize >= dimmSize) *BR1(INTERNAL_MEM_MAP_ADDR) = temp; else *BR1(INTERNAL_MEM_MAP_ADDR) = (temp & OR_OPTIONS_BITS_MSK) | dimmSize; /* configure the base/option registers for the DIMM */ if ( dimmSize > MEM_SIZE_0MB) { temp = *OR2(INTERNAL_MEM_MAP_ADDR); *OR2(INTERNAL_MEM_MAP_ADDR) = ((~(dimmSize / 2) + 1) & OR_AM_MSK) | (temp & OR_OPTIONS_BITS_MSK); temp = *OR3(INTERNAL_MEM_MAP_ADDR); *OR3(INTERNAL_MEM_MAP_ADDR) = ((~(dimmSize / 2) + 1) & OR_AM_MSK) | (temp & OR_OPTIONS_BITS_MSK); if ( dimmSize > dramSize ) { temp = *BR2(INTERNAL_MEM_MAP_ADDR) | BR_V; *BR2(INTERNAL_MEM_MAP_ADDR) = (temp & OR_OPTIONS_BITS_MSK); temp = *BR3(INTERNAL_MEM_MAP_ADDR) | BR_V; *BR3(INTERNAL_MEM_MAP_ADDR) = (temp & OR_OPTIONS_BITS_MSK) | (dimmSize / 2); } else { temp = *BR2(INTERNAL_MEM_MAP_ADDR) | BR_V; *BR2(INTERNAL_MEM_MAP_ADDR) = (temp & OR_OPTIONS_BITS_MSK) | dramSize; temp = *BR3(INTERNAL_MEM_MAP_ADDR) | BR_V; *BR3(INTERNAL_MEM_MAP_ADDR) = (temp & OR_OPTIONS_BITS_MSK) | (dramSize + (dimmSize/2)); } } /* if QSPAN is present, then enable the valid bits for the PCI banks */ temp = *(UINT32 *)(DPRAM_QSPAN_PRSNT); if (temp) { temp = *BR5(INTERNAL_MEM_MAP_ADDR) | BR_V; *BR5(INTERNAL_MEM_MAP_ADDR) = temp; temp = *BR6(INTERNAL_MEM_MAP_ADDR) | BR_V; *BR6(INTERNAL_MEM_MAP_ADDR) = temp; } }
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