master_main_old_原来机场算法.c

DSP编程

  
  // Write the next mode in Master-DSP 
  target_mode= *(unsigned int *)ADDR_OF_READ_MODE;
  if((++target_mode)>4) target_mode=1;
  *(unsigned int *)ADDR_OF_WRITE_MODE = target_mode;
  
  edma_null_init();
  edma_start(ADDR_OF_REC_FROM_FIFO,(int)(ImgBufferArea), CHANNEL_OF_REC_FROM_FIFO, 
             FIXED_ADDR_MODE, INCREMENT_ADDR_MODE, 1, IMG_SIZE_IN_WORD);
  edma_start(ADDR_OF_REC_FROM_FIFO,(int)(TrashArea), CHANNEL_OF_REC_FROM_FIFO_TRASH, 
             FIXED_ADDR_MODE, INCREMENT_ADDR_MODE, 1, IMG_SIZE_IN_WORD);
  edma_start((int)(seg_buff),ADDR_OF_TRANS_TO_DSP1,CHANNEL_OF_TRANS_TO_DSP1,
             INCREMENT_ADDR_MODE,FIXED_ADDR_MODE, 1, IMG_SIZE_IN_WORD/2);
  edma_start((int)(seg_buff),ADDR_OF_TRANS_TO_DSP2,CHANNEL_OF_TRANS_TO_DSP2,
             INCREMENT_ADDR_MODE,FIXED_ADDR_MODE, 1, IMG_SIZE_IN_WORD/2);
             
//  edma_start((int)(ImgBufferArea),ADDR_OF_DUALPORT_RAM, CHANNEL_OF_TARNS_TO_DPRAM,
//             INCREMENT_ADDR_MODE, INCREMENT_ADDR_MODE, 1, IMG_SIZE_IN_WORD);
  *(unsigned volatile int *)QDMA_OPT = (QDMA_PRI<<PRI) + (1<<SUM) + (1<<DUM) + (1<<TCINT)  
                                     + (CHANNEL_OF_TARNS_TO_DPRAM%16<<TCC)+ (CHANNEL_OF_TARNS_TO_DPRAM/16<<TCCM) + (1<<FS);
  *(unsigned volatile int *)QDMA_SRC = (int)img_buff;
  *(unsigned volatile int *)QDMA_DST = ADDR_OF_DUALPORT_RAM;
  *(unsigned volatile int *)QDMA_CNT = IMG_SIZE_IN_WORD;	
  *(unsigned volatile int *)CIERL |= (1<<CHANNEL_OF_TARNS_TO_DPRAM);
									
             
  edma_start((int)(ImgBufferArea),ADDR_OF_TRANS_TO_HOTLINK,CHANNEL_OF_TRANS_TO_HOTLINK,
             INCREMENT_ADDR_MODE, FIXED_ADDR_MODE, 1, IMG_SIZE_IN_WORD);
  
  /* Wait: the slave-DSPs */
#ifdef TEST_DSP1_2  
  mcbsp_test_init(McBSP1_TO_DSP12);
  mcbsp_write(RESET_OK, McBSP1_TO_DSP12);
  delay_msec(2, 100);
  do
  {temp = mcbsp_read(McBSP1_TO_DSP12);}
  while(temp != RESET_OK);
  for(i=0;i<3;i++)
  {
    LED_OFF();
    delay_msec(2, 1);
    LED_ON();
    delay_msec(2, 1);
  }
  
  /* Initial the McBSP registers */
  mcbsp_init(McBSP1_TO_DSP12, 5);     //modify the ClkGdv value in SRGR
  
  RESET_BIT(McBSP_SPCR(McBSP1_TO_DSP12), RRST);
  SPORT_edmar_init((int)&message_rec, McBSP1_TO_DSP12, MSG_SIZE);
  SET_BIT(McBSP_SPCR(McBSP1_TO_DSP12), RRST);
#endif  
  
  *(unsigned volatile int *)McBSP_SPCR(McBSP0_TO_CONTROLLER) = 0;
  *(unsigned volatile int *)McBSP_SRGR(McBSP0_TO_CONTROLLER) = ((1<<CLKSM) + 
                                       (0<<FSGM) + (16<<FPER) + (14<<CLKGDV));
  *(unsigned volatile int *)McBSP_PCR(McBSP0_TO_CONTROLLER) = 0xA00;
  *(unsigned volatile int *)McBSP_RCR(McBSP0_TO_CONTROLLER) = ((1<<FIG) + 
                                      (2<<WDLEN1) + (0<<FRLEN1) + (0<<DATDLY));
  *(unsigned volatile int *)McBSP_XCR(McBSP0_TO_CONTROLLER) = ((1<<FIG) + 
                                      (2<<WDLEN1) + (0<<FRLEN1) + (0<<DATDLY));	
  *(unsigned volatile int *)McBSP_SPCR(McBSP0_TO_CONTROLLER) |= (1<<GRST);
  
  for (i=0; i<0x10; i++);
  
  *(unsigned volatile int *)McBSP_SPCR(McBSP0_TO_CONTROLLER) |= ((1<<FREE) + 
                                                        (1<<FRST) + (1<<RRST));
  
  /* Initial the Timer register for interrupt */
  slave1_time = 9999999;
  slave2_time = 9999999;
  C6000_Set_Up_TIMER_Tick_In_Microseconds(1000, 1);
  
  /* Open the needed Interrupt */
  *(volatile unsigned  int *)MUXH = 0x82D2D43;          //Enable RINT0 to INT13
  ICR = IFR | ((1<<IF15)+(1<<IF13)+(1<<IF8)+(1<<IF6));  //+(1<<IF7)+(1<<IF4)
  IER |= ((1<<IE15)+(1<<IE13)+(1<<IE8)+(1<<IE6));       //+(1<<IE7)+(1<<IE4)
  CSR |= (1<<GIE);
  
}


/*-------------------------------------------*/
/* FUNCTION: process the received message    */
/*-------------------------------------------*/
void proc_msg()
{ 
  switch(message_rec.MsgType)
  {      
    case MSG_TYPE_PROC_RESULT:      
       if(message_rec.SrcdspId==SLAVE_ONE)
       {
         slave1_time = 9999999;
         RecfromDsp1_flag = 1;
         RecRstArea[1].Target_x = message_rec.MsgTypeContent.PRMsg.Target_x;
         RecRstArea[1].Target_y = message_rec.MsgTypeContent.PRMsg.Target_y;
         RecRstArea[1].Target_Cof = message_rec.MsgTypeContent.PRMsg.Target_Cof;
         
       }
       else if(message_rec.SrcdspId==SLAVE_TWO)
       {
         slave2_time = 9999999;
         RecfromDsp2_flag = 1;
         RecRstArea[2].Target_x = message_rec.MsgTypeContent.PRMsg.Target_x;
         RecRstArea[2].Target_y = message_rec.MsgTypeContent.PRMsg.Target_y;
         RecRstArea[2].Target_Cof = message_rec.MsgTypeContent.PRMsg.Target_Cof;
      
       }
       break;
       
    case MSG_TYPE_ACK_STATE:
       if(message_rec.SrcdspId==SLAVE_ONE)
       {
         FIFO_01_HIGH();
         FIFO_01_LOW();
         SET_BIT(ESRL,CHANNEL_OF_TRANS_TO_DSP1);
       }           
       else if(message_rec.SrcdspId==SLAVE_TWO)
       {
         FIFO_02_HIGH();
         FIFO_02_LOW();
         SET_BIT(ESRL,CHANNEL_OF_TRANS_TO_DSP2);
       }  
       break;
       
    default: break;
  }    
  SPORT_edmar_init((int)&message_rec, McBSP1_TO_DSP12, MSG_SIZE);
}

/*------------------------------------*/
/*  The interrupt prog as follows:    */
/*------------------------------------*/
interrupt void RecOrg_isr()
{
  if(RawImgRxEnable)
  {
    BusEnable = 0;   //Lock the System Bus
    SET_BIT(ESRL,CHANNEL_OF_REC_FROM_FIFO); //trig rec EDMA
  }
  else
  {
    BusEnable = 0;   //Lock the System Bus
    SET_BIT(ESRL,CHANNEL_OF_REC_FROM_FIFO_TRASH); //trig rec EDMA
  }
}

/*------------------------------------*/
interrupt void RINT0_isr()
{
//  control_rec = *(unsigned volatile int *)McBSP_DRR(McBSP0_TO_CONTROLLER);
//  RecMsg_flag = 1;
}

/*------------------------------------*/
interrupt void timer1_isr()
{
  if((--slave1_time)<=0)
  {
    slave1_time = 9999999;
    dsp_s.Dsp1State = bad;
    TransToDsp1_flag = 1;
    RecfromDsp1_flag = 1;
  }
  if((--slave2_time)<=0)
  {
    slave2_time = 9999999;
    dsp_s.Dsp2State = bad;
    TransToDsp2_flag = 1;
    RecfromDsp2_flag = 1;
  }
}

/*------------------------------------*/
interrupt void edma_isr()
{
  if(GET_BIT(CIPRL,McBSPr_EDMA_Ch[McBSP1_TO_DSP12]))
  {
    REG_WRITE(CIPRL,1<<McBSPr_EDMA_Ch[McBSP1_TO_DSP12]);
    proc_msg();
  }
  
  else if(GET_BIT(CIPRL,CHANNEL_OF_REC_FROM_FIFO))
  {
    REG_WRITE(CIPRL,1<<CHANNEL_OF_REC_FROM_FIFO);
    
    edma_start(ADDR_OF_REC_FROM_FIFO,(int)(ImgBufferArea), CHANNEL_OF_REC_FROM_FIFO, 
               FIXED_ADDR_MODE, INCREMENT_ADDR_MODE, 1, IMG_SIZE_IN_WORD);
    RawImgRxEnable = 0;
    BusEnable = 1;         //Unlock the System Bus
    RawImgRxCnt++;
    
#ifdef IS_TEST_TIME    
    if(RawImgRxCnt==1)
    {
      timer_start(0);
      tips0_start = TIMER_READ(0);
    }
#endif
  }
  
  else if(GET_BIT(CIPRL,CHANNEL_OF_REC_FROM_FIFO_TRASH))
  {
    REG_WRITE(CIPRL,1<<CHANNEL_OF_REC_FROM_FIFO_TRASH);
    
    edma_start(ADDR_OF_REC_FROM_FIFO,(int)(TrashArea), CHANNEL_OF_REC_FROM_FIFO_TRASH, 
               FIXED_ADDR_MODE, INCREMENT_ADDR_MODE, 1, IMG_SIZE_IN_WORD);               
    BusEnable = 1;         //Unlock the System Bus
    Trash_Count++;
  }
  
  else if(GET_BIT(CIPRL,CHANNEL_OF_TRANS_TO_DSP1))
  {    
    REG_WRITE(CIPRL,1<<CHANNEL_OF_TRANS_TO_DSP1);        
    edma_start((int)(seg_buff),ADDR_OF_TRANS_TO_DSP1,CHANNEL_OF_TRANS_TO_DSP1,
               INCREMENT_ADDR_MODE,FIXED_ADDR_MODE, 1, IMG_SIZE_IN_WORD/2);
    TransToDsp1_flag = 1;
  }
  
  else if(GET_BIT(CIPRL,CHANNEL_OF_TRANS_TO_DSP2))
  {
    REG_WRITE(CIPRL,1<<CHANNEL_OF_TRANS_TO_DSP2);   
    edma_start((int)(seg_buff),ADDR_OF_TRANS_TO_DSP2,CHANNEL_OF_TRANS_TO_DSP2,
               INCREMENT_ADDR_MODE,FIXED_ADDR_MODE, 1, IMG_SIZE_IN_WORD/2);
    TransToDsp2_flag = 1;
  }
  
  else if(GET_BIT(CIPRL,CHANNEL_OF_INTERNAL_EXCH))
  {
    REG_WRITE(CIPRL,1<<CHANNEL_OF_INTERNAL_EXCH);
    exch_flag = 1;
  }
  
  else if(GET_BIT(CIPRL,CHANNEL_OF_TARNS_TO_DPRAM))
  {   
    REG_WRITE(CIPRL,1<<CHANNEL_OF_TARNS_TO_DPRAM);
    
    edma_start((int)(img_buff),ADDR_OF_DUALPORT_RAM, CHANNEL_OF_TARNS_TO_DPRAM,
               INCREMENT_ADDR_MODE, INCREMENT_ADDR_MODE, 1, IMG_SIZE_IN_WORD);
    RawImgRxEnable = 1;
    TransToDpram_flag = 1;
    RstImgTxCnt++;
    
#ifdef IS_TEST_TIME    
    tips0 = timer_count2us(TIMER_READ(0)-tips0_start);
    temp_time = tips0-test_time.TotalTime;
    if(test_time.MaxTime<temp_time)
      test_time.MaxTime = temp_time;
    if(test_time.MinTime>temp_time)
      test_time.MinTime = temp_time;
    test_time.TotalTime = tips0;
    test_time.AverageTime = test_time.TotalTime/RstImgTxCnt;
#endif
  }
  
  else if(GET_BIT(CIPRL,CHANNEL_OF_TRANS_TO_HOTLINK))
  {
    REG_WRITE(CIPRL,1<<CHANNEL_OF_TRANS_TO_HOTLINK);
        
    edma_start((int)(ImgBufferArea),ADDR_OF_TRANS_TO_HOTLINK,CHANNEL_OF_TRANS_TO_HOTLINK,
               INCREMENT_ADDR_MODE, FIXED_ADDR_MODE, 1, IMG_SIZE_IN_WORD);  
    RawImgRxEnable = 1;
    TransToHotlink_flag = 1;
    RstImgTxCnt++;
  }  
}

/******************************** End File **************************************/