emif.h

DSP编程

/* Define EMIF Registers  */

#define EMIFA_GCR 		0x1800000	/* Address of EMIFA global control		*/
#define EMIFA_CE0		0x1800008	/* Address of EMIFA CE0 control			*/
#define EMIFA_CE0SEC    0x1800048   /*Address of EMIFA CE0 space secondary control*/

#define EMIFA_CE1		0x1800004	/* Address of EMIFA CE1 control			*/
#define EMIFA_CE1SEC    0x1800044   /*Address of EMIFA CE1 space secondary control*/

#define EMIFA_CE2		0x1800010	/* Address of EMIFA CE2 control			*/
#define EMIFA_CE2SEC    0x1800050   /*Address of EMIFA CE2 space secondary control*/

#define EMIFA_CE3		0x1800014	/* Address of EMIFA CE3 control			*/
#define EMIFA_CE3SEC    0x1800054   /*Address of EMIFA CE3 space secondary control*/

#define EMIFA_SDCTRL	0x1800018	/* Address of EMIFA SDRAM control		*/
#define EMIFA_SDRP		0x180001c	/* Address of EMIFA SDRM refresh period	*/
#define EMIFA_SDEXT		0x1800020	/* Address of EMIFA SDRAM extension		*/


#define EMIFB_GCR 		0x1A80000	/* Address of EMIFB global control		*/
#define EMIFB_CE0		0x1A80008	/* Address of EMIFB CE0 control			*/
#define EMIFB_CE0SEC    0x1A80048   /*Address of EMIFB CE0 space secondary control*/

#define EMIFB_CE1		0x1A80004	/* Address of EMIFB CE1 control			*/
#define EMIFB_CE1SEC    0x1A80044   /*Address of EMIFB CE1 space secondary control*/

#define EMIFB_CE2		0x1A80010	/* Address of EMIFB CE2 control			*/
#define EMIFB_CE2SEC    0x1A80050   /*Address of EMIFB CE2 space secondary control*/

#define EMIFB_CE3		0x1A80014	/* Address of EMIFB CE3 control			*/
#define EMIFB_CE3SEC    0x1A80054   /*Address of EMIFB CE3 space secondary control*/

#define EMIFB_SDCTRL	0x1A80018	/* Address of EMIFB SDRAM control		*/
#define EMIFB_SDRP		0x1A8001c	/* Address of EMIFB SDRM refresh period	*/
#define EMIFB_SDEXT		0x1A80020	/* Address of EMIFB SDRAM extension		*/

/* EMIF Global Control Register (GBLCTL) */
#define CLK6EN                   3
#define CLK4EN                   4
#define EK1EN                    5
#define EK1HZ                    6
#define NOHOLD                   7
#define HOLDA                    8 
#define HOLD                     9
#define ARDY                    10
#define BUSREQ                  11
#define BRMODE                  13
#define EK2EN                   16
#define EK2HZ                   17
#define EK2RATE                 18

/*EMIF CE Space Control Register (CExCTL)*/
#define READHOLD                 0       /* Hold width   */
#define WRITEHOLDMSB             3
#define MTYPE                    4       /* Memory type of the corresponding CE spaces      */
#define READSTROBE               8       /* The width of read strobe (/ARE) in clock cycles */
#define TA                      14       /* Turn-around time                                */
#define READSETUP               16       /* Setup width  */
#define WRITEHOLD               20       /* Hold width   */
#define WRITESTROBE             22       /* The width of write strobe (/AWE) in clock cycles*/
#define WRITESETUP              28       /* Setup width  */

/* CE Space Secondary Control Register (CExSEC) – TMS320C64x Only */
#define SYNCRL                   0       /* Synchronous interface data read latency  */
#define SYNCWL                   2       /* Synchronous interface data write latency */
#define CEEXT                    4       /* CE extension register                    */
#define RENEN                    5       /* Read Enable Enable                       */
#define SNCCLK                   6       /* Synchronization Clock                    */