📄 option.inc.bak
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;===========================================
; NAME: OPTION.INC
; DESC: Configuration options for .S files
; HISTORY:
; 02.28.2002: ver 0.0
; 03.11.2003: ver 0.0 attached for 2440.
;===========================================
;Start address of each stacks,
_STACK_BASEADDRESS EQU 0x33ff8000
_MMUTT_STARTADDRESS EQU 0x33ff8000
_ISR_STARTADDRESS EQU 0x33ffff00
GBLL PLL_ON_START
PLL_ON_START SETL {TRUE}
GBLL ENDIAN_CHANGE
ENDIAN_CHANGE SETL {FALSE}
GBLA ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH SETA 16
;BUSWIDTH = 16,32
GBLA BUSWIDTH ;max. bus width for the GPIO configuration
BUSWIDTH SETA 32
CLKDIV_VAL EQU (5) ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 0x5=1:4:8, 7=1:3:6
GBLA FCLK
FCLK SETA 400000000
GBLA UCLK
UCLK SETA 48000000
[ FCLK = 533000000
M_MDIV EQU 214 ;214/3/0, Fin=12.0MHz Fout=533MHz
M_PDIV EQU 3
M_SDIV EQU 0
]
[ FCLK = 400000000
M_MDIV EQU 92 ;212/4/0, 212/1/1, Fin=12.0MHz Fout=400MHz
M_PDIV EQU 1
M_SDIV EQU 0
;M_MDIV EQU 117
;M_PDIV EQU 4
;M_SDIV EQU 0
]
[ FCLK = 203200000
M_MDIV EQU 246 ;Fin=12.0MHz Fout=203.2MHz
M_PDIV EQU 13
M_SDIV EQU 0
]
[ UCLK = 48000000
U_MDIV EQU 56 ;Fin=12.0MHz Fout=48MHz
U_PDIV EQU 2
U_SDIV EQU 2
;U_MDIV EQU 32 ;Fin=12.0MHz Fout=48MHz
;U_PDIV EQU 2
;U_SDIV EQU 2
]
[ UCLK = 96000000
U_MDIV EQU 56 ;Fin=12.0MHz Fout=96MHz
U_PDIV EQU 2
U_SDIV EQU 1
]
END
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