top_avr_core_sim.vhd

AVR单片机的源代码

--************************************************************************************************
-- Top entity for AVR microcontroller (for simulation)
-- Version 1.4
-- Designed by Ruslan Lepetenok 
-- Modified 20.05.2003
--************************************************************************************************

library IEEE;
use IEEE.std_logic_1164.all;

use WORK.AVRuCPackage.all;

entity top_avr_core_sim is generic(InsertWaitSt : boolean := FALSE;
	         					   RAMSize      : positive := 128);
		                    port(
                                ireset : in std_logic;
                                cp2    : in std_logic;
	 	 
                                porta  : inout std_logic_vector(7 downto 0);
                                portb  : inout std_logic_vector(7 downto 0);
	                            -- UART 
	                            rxd    : in  std_logic;
	                            txd    : out std_logic;
                                -- External interrupt inputs
								nINT0  : in  std_logic;
								nINT1  : in  std_logic;
								nINT2  : in  std_logic;
								nINT3  : in  std_logic;
								INT4   : in  std_logic;
								INT5   : in  std_logic;
								INT6   : in  std_logic;
								INT7   : in  std_logic
								);
end top_avr_core_sim;

architecture Struct of top_avr_core_sim is

component pport is 
	generic(
	        PORTX_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
	        DDRX_Adr  : std_logic_vector(IOAdrWidth-1 downto 0);
			PINX_Adr  : std_logic_vector(IOAdrWidth-1 downto 0)
			);
	port(
	                   -- AVR Control
               ireset     : in std_logic;
               cp2	      : in std_logic;
               adr        : in std_logic_vector(5 downto 0);
               dbus_in    : in std_logic_vector(7 downto 0);
               dbus_out   : out std_logic_vector(7 downto 0);
               iore       : in std_logic;
               iowe       : in std_logic;
               out_en     : out std_logic; 
			            -- External connection
			   portx      : out std_logic_vector(7 downto 0);
			   ddrx       : out std_logic_vector(7 downto 0);
			   pinx       : in  std_logic_vector(7 downto 0));
end component;

component external_mux is port (
		  ramre              : in  std_logic;
		  dbus_out           : out std_logic_vector (7 downto 0);
		  ram_data_out       : in  std_logic_vector (7 downto 0);
		  io_port_bus        : in  ext_mux_din_type;
		  io_port_en_bus     : in  ext_mux_en_type;
          irqack             : in  std_logic;
          irqackad           : in  std_logic_vector(4 downto 0);		  
		  ind_irq_ack        : out std_logic_vector(22 downto 0)		  
		  );
end component;

component Service_Module is port(
	                   -- AVR Control
               ireset         : in  std_logic;
               cp2	          : in  std_logic;
               adr            : in  std_logic_vector(5 downto 0);
               dbus_in        : in  std_logic_vector(7 downto 0);
               dbus_out       : out std_logic_vector(7 downto 0);
               iore           : in  std_logic;
               iowe           : in  std_logic;
               out_en         : out std_logic; 
			        -- SLEEP mode signals
			   sleep_en       : out std_logic;
		   	        -- SRAM control signals
			   ESRAM_en       : out std_logic;
			   ESRAM_WS       : out std_logic;
			   	    --IRQ
               ExtInt_IRQ     : out std_logic_vector(7 downto 0);
			   ExtInt_IRQ_Ack : in  std_logic_vector(3 downto 0);
			   
			   -- External interrupts (inputs)
			   Ext_Int_In     : in  std_logic_vector(7 downto 0));
end component;

component RAMDataReg is port(	                   
               ireset      : in  std_logic;
               cp2	       : in  std_logic;
               cpuwait     : in  std_logic;
			   RAMDataIn   : in  std_logic_vector(7 downto 0);
			   RAMDataOut  : out std_logic_vector(7 downto 0)
	                     );
end component;


-- SIMPLE TIMER **********************************
component simple_timer is port(
ireset        : in std_logic;
cp2           : in std_logic;
irqline       : out std_logic;
timer_irqack  : in std_logic
							  );
end component;
-- ***********************************************


component Timer_Counter is port(
	                   -- AVR Control
               ireset         : in std_logic;
               cp2	          : in std_logic;
               adr            : in std_logic_vector(5 downto 0);
               dbus_in        : in std_logic_vector(7 downto 0);
               dbus_out       : out std_logic_vector(7 downto 0);
               iore           : in std_logic;
               iowe           : in std_logic;
               out_en         : out std_logic; 

                       --Timer/Counters
               EXT1           : in std_logic;
               EXT2           : in std_logic;
			   Tosc1	      : in std_logic;
			   OC0_PWM0       : out std_logic;
			   OC1A_PWM1A     : out std_logic;
			   OC1B_PWM1B     : out std_logic;
			   OC2_PWM2       : out std_logic;
			   		   
			           --IRQ
               TC0OvfIRQ      : out std_logic;
			   TC0OvfIRQ_Ack  : in std_logic;
			   TC0CmpIRQ      : out std_logic;
			   TC0CmpIRQ_Ack  : in std_logic;
			   TC2OvfIRQ      : out std_logic;
			   TC2OvfIRQ_Ack  : in std_logic;
			   TC2CmpIRQ      : out std_logic;
			   TC2CmpIRQ_Ack  : in std_logic;
			   TC1OvfIRQ      : out std_logic;
			   TC1OvfIRQ_Ack  : in std_logic;
			   TC1CmpAIRQ     : out std_logic;
			   TC1CmpAIRQ_Ack : in std_logic;
			   TC1CmpBIRQ     : out std_logic;
			   TC1CmpBIRQ_Ack : in std_logic;			   
			   TC1ICIRQ       : out std_logic;
			   TC1ICIRQ_Ack   : in std_logic);
end component;


--*************** UART ***************************
component uart is port(
	                   -- AVR Control
               ireset     : in std_logic;
               cp2	      : in std_logic;
               adr        : in std_logic_vector(5 downto 0);
               dbus_in    : in std_logic_vector(7 downto 0);
               dbus_out   : out std_logic_vector(7 downto 0);
               iore       : in std_logic;
               iowe       : in std_logic;
               out_en     : out std_logic; 

                       --UART
               rxd        : in std_logic;
               rx_en      : out std_logic;
               txd        : out std_logic;
               tx_en      : out std_logic;

                       --IRQ
               txcirq     : out std_logic;
               txc_irqack : in std_logic;
               udreirq    : out std_logic;
			   rxcirq     : out std_logic);
end component;


component PROM is port (
address_in : in  std_logic_vector (15 downto 0);
data_out   : out std_logic_vector (15 downto 0));
end component;

component DataRAM is 
		  generic(RAMSize :positive);
	      port (
          cp2         : in std_logic;
  	      address     : in  std_logic_vector (LOG2(RAMSize)-1 downto 0);
		  ramwe		  : in  std_logic;
		  din         : in  std_logic_vector (7 downto 0);
		  dout        : out	std_logic_vector (7 downto 0));
end component;

component CPUWaitGenerator is
			   generic(InsertWaitSt : boolean);
	           port(
	           ireset  : in  std_logic;
			   cp2     : in  std_logic;
			   ramre   : in  std_logic;
			   ramwe   : in  std_logic;
			   cpuwait : out std_logic                 
			        );
end component;


-- Core itself
component avr_core is port
(

cp2      : in std_logic;
ireset   : in std_logic;
cpuwait  : in std_logic;

-- PROGRAM MEMORY PORTS
pc       : out std_logic_vector (15 downto 0);   
inst     : in std_logic_vector (15 downto 0);	

-- I/O REGISTERS PORTS
adr      : out std_logic_vector (5 downto 0); 	
iore     : out std_logic;                       
iowe     : out std_logic;						

-- DATA MEMORY PORTS
ramadr   : out std_logic_vector (15 downto 0);
ramre    : out std_logic;
ramwe    : out std_logic;

dbusin   : in std_logic_vector (7 downto 0);
dbusout  : out std_logic_vector (7 downto 0);

-- INTERRUPTS PORT
irqlines : in std_logic_vector (22 downto 0);
irqack   : out std_logic;
irqackad : out std_logic_vector(4 downto 0)

);

end component;


-- ############################## Signals connected directly to the core ##########################################

signal sg_core_cpuwait  : std_logic :='0';                    

-- Program memory
signal sg_core_pc   : std_logic_vector (15 downto 0):=(others=>'0'); -- PROM address
signal sg_core_inst : std_logic_vector (15 downto 0):=(others=>'0'); -- PROM data

-- I/O registers
signal sg_core_adr  : std_logic_vector (5 downto 0):=(others=>'0');
signal sg_core_iore : std_logic :='0';                    
signal sg_core_iowe : std_logic :='0';

-- Data memery
signal sg_core_ramadr : std_logic_vector (15 downto 0):=(others=>'0');
signal sg_core_ramre  : std_logic :='0';
signal sg_core_ramwe  : std_logic :='0';

signal sg_core_dbusin   : std_logic_vector (7 downto 0):=(others=>'0');
signal sg_core_dbusout  : std_logic_vector (7 downto 0):=(others=>'0');

-- Interrupts
signal sg_core_irqlines : std_logic_vector(22 downto 0) :=(others=>'0');
signal sg_core_irqack   : std_logic :='0';
signal sg_core_irqackad : std_logic_vector(4 downto 0) :=(others=>'0');

-- ###############################################################################################################

-- ############################## Signals connected directly to the SRAM controller ###############################

signal sg_ram_din       : std_logic_vector (7 downto 0):=(others=>'0');
signal sg_ram_dout      : std_logic_vector (7 downto 0):=(others=>'0');

-- ###############################################################################################################


-- ############################## Signals connected directly to the I/O registers ################################
-- PortA
signal sg_porta_dbusout : std_logic_vector (7 downto 0) := (others => '0');
signal sg_porta_out_en  : std_logic := '0';

-- PortB
signal sg_portb_dbusout : std_logic_vector (7 downto 0) := (others => '0');
signal sg_portb_out_en : std_logic := '0';

-- UART
signal sg_uart_dbusout : std_logic_vector (7 downto 0) := (others => '0');
signal sg_uart_out_en  : std_logic := '0';

signal sg_uart_tx_en  : std_logic := '0';
signal sg_uart_rx_en  : std_logic := '0';