multlib.vhd

ARM7的源代码

----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Lesser General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
--
--  See the file COPYING.LGPL for the full details of the license.


-----------------------------------------------------------------------------
-- Package: 	multlib
-- File:	multlib.vhd
-- Author:	Jiri Gaisler - Gaisler Research
-- Description:	A set of multipliers generated from the Arithmetic Module
--		Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.leon_iface.all;

package multlib is

component mul_17_17
  port (
    clk  : in clk_type;
    holdn: in std_logic;
    x    : in  std_logic_vector(16 downto 0);
    y    : in  std_logic_vector(16 downto 0);
    p    : out std_logic_vector(33 downto 0)
  ); 
end component;

component mul_33_9
  port (
    x    : in  std_logic_vector(32 downto 0);
    y    : in  std_logic_vector(8 downto 0);
    p    : out std_logic_vector(41 downto 0)
  ); 
end component;

component mul_33_17
  port (
    x    : in  std_logic_vector(32 downto 0);
    y    : in  std_logic_vector(16 downto 0);
    p    : out std_logic_vector(49 downto 0)
  ); 
end component;

component mul_33_33
  port (
    x    : in  std_logic_vector(32 downto 0);
    y    : in  std_logic_vector(32 downto 0);
    p    : out std_logic_vector(65 downto 0)
  ); 
end component;

component add32
  port(
    x	 : in  std_logic_vector(31 downto 0);
    y	 : in  std_logic_vector(31 downto 0);
    ci	 : in  std_logic;
    s	 : out std_logic_vector(31 downto 0);
    co	 : out std_logic
  );
end component;

end multlib;


------------------------------------------------------------
-- START: Entities used within the Modified Booth Recoding
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity PP_LOW is
port
(
		ONEPOS, ONENEG, TWONEG: in std_logic;
		INA, INB: in std_logic;
		PPBIT: out std_logic
);
end PP_LOW;
library ieee;
use ieee.std_logic_1164.all;
entity PP_MIDDLE is
port
(
		ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
		INA, INB, INC, IND: in std_logic;
		PPBIT: out std_logic
);
end PP_MIDDLE;
library ieee;
use ieee.std_logic_1164.all;
entity PP_HIGH is
port
(
		ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
		INA, INB: in std_logic;
		PPBIT: out std_logic
);
end PP_HIGH;
library ieee;
use ieee.std_logic_1164.all;
entity R_GATE is
port
(
		INA, INB, INC: in std_logic;
		PPBIT: out std_logic
);
end R_GATE;
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port
(
		INA, INB, INC: in std_logic;
		TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end DECODER;
------------------------------------------------------------
-- END: Entities used within the Modified Booth Recoding
------------------------------------------------------------

------------------------------------------------------------
-- START: Entities within the Wallace-tree
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity FULL_ADDER is
port
(
	DATA_A, DATA_B, DATA_C: in std_logic;
	SAVE, CARRY: out std_logic
);
end FULL_ADDER;
library ieee;
use ieee.std_logic_1164.all;
entity HALF_ADDER is
port
(
	DATA_A, DATA_B: in std_logic;
	SAVE, CARRY: out std_logic
);
end HALF_ADDER;
------------------------------------------------------------
-- END: Entities within the Wallace-tree
------------------------------------------------------------

------------------------------------------------------------
-- START: Entities within the DBLC-tree
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity INVBLOCK is
port
(
	GIN,PHI:in std_logic;
	GOUT:out std_logic
);
end INVBLOCK;

library ieee;
use ieee.std_logic_1164.all;
entity XXOR1 is
port
(
	A,B,GIN,PHI:in std_logic;
	SUM:out std_logic
);
end XXOR1;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK0 is
port
(
	A,B,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end BLOCK0;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1 is
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end BLOCK1;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2 is
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end BLOCK2;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1A is
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end BLOCK1A;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2A is
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end BLOCK2A;

library ieee;
use ieee.std_logic_1164.all;
entity PRESTAGE_64 is
port
(
	A: in std_logic_vector(0 to 63);
	B: in std_logic_vector(0 to 63);
	CIN: in std_logic;
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 63);
	GOUT: out std_logic_vector(0 to 64)
);
end PRESTAGE_64;

library ieee;
use ieee.std_logic_1164.all;
entity DBLC_0_64 is
port
(
	PIN: in std_logic_vector(0 to 63);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 62);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_0_64;

library ieee;
use ieee.std_logic_1164.all;
entity DBLC_1_64 is
port
(
	PIN: in std_logic_vector(0 to 62);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 60);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_1_64;

library ieee;
use ieee.std_logic_1164.all;
entity DBLC_2_64 is
port
(
	PIN: in std_logic_vector(0 to 60);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 56);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_2_64;

library ieee;
use ieee.std_logic_1164.all;
entity DBLC_3_64 is
port
(
	PIN: in std_logic_vector(0 to 56);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 48);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_3_64;

library ieee;
use ieee.std_logic_1164.all;
entity DBLC_4_64 is
port
(
	PIN: in std_logic_vector(0 to 48);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 32);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_4_64;

library ieee;
use ieee.std_logic_1164.all;
entity DBLC_5_64 is
port
(
	PIN: in std_logic_vector(0 to 32);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 0);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_5_64;

library ieee;
use ieee.std_logic_1164.all;
entity XORSTAGE_64 is
port
(
	A: in std_logic_vector(0 to 63);
	B: in std_logic_vector(0 to 63);
	PBIT, PHI: in std_logic;
	CARRY: in std_logic_vector(0 to 64);
	SUM: out std_logic_vector(0 to 63);
	COUT: out std_logic
);
end XORSTAGE_64;

library ieee;
use ieee.std_logic_1164.all;
entity DBLCTREE_64 is
port
(
	PIN:in std_logic_vector(0 to 63);
	GIN:in std_logic_vector(0 to 64);
	PHI:in std_logic;
	GOUT:out std_logic_vector(0 to 64);
	POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_64;

library ieee;
use ieee.std_logic_1164.all;
entity DBLCADDER_64_64 is
port
(
	OPA:in std_logic_vector(0 to 63);
	OPB:in std_logic_vector(0 to 63);
	CIN:in std_logic;
	PHI:in std_logic;
	SUM:out std_logic_vector(0 to 63);
	COUT:out std_logic
);
end DBLCADDER_64_64;

------------------------------------------------------------
-- END: Entities within the DBLC-tree
------------------------------------------------------------

------------------------------------------------------------
-- START: Architectures used with the Modified Booth recoding
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
architecture PP_LOW of PP_LOW is
begin
	PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG;
end PP_LOW;
library ieee;
use ieee.std_logic_1164.all;
architecture PP_MIDDLE of PP_MIDDLE is
begin
	PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG)));
end PP_MIDDLE;
library ieee;
use ieee.std_logic_1164.all;
architecture PP_HIGH of PP_HIGH is
begin
	PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG));
end PP_HIGH;
library ieee;
use ieee.std_logic_1164.all;
architecture R_GATE of R_GATE is
begin
	PPBIT <= (not(INA and INB)) and INC;
end R_GATE;
library ieee;
use ieee.std_logic_1164.all;
architecture DECODER of DECODER is
begin
	TWOPOS <= not(not(INA and INB and (not INC)));
	TWONEG <= not(not((not INA) and (not INB) and INC));
	ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA);
	ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA));
end DECODER;
--
------------------------------------------------------------
-- END: Architectures used with the Modified Booth recoding
------------------------------------------------------------

------------------------------------------------------------
-- START: Architectures used with the Wallace-tree
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
architecture FULL_ADDER of FULL_ADDER is
	signal TMP: std_logic;
begin
	TMP <= DATA_A xor DATA_B;
	SAVE <= TMP xor DATA_C;
	CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B)));
end FULL_ADDER;
library ieee;
use ieee.std_logic_1164.all;
architecture HALF_ADDER of HALF_ADDER is
begin
	SAVE <= DATA_A xor DATA_B;
	CARRY <= DATA_A and DATA_B;
end HALF_ADDER;
------------------------------------------------------------
-- END: Architectures used with the Wallace-tree
------------------------------------------------------------

------------------------------------------------------------
-- START: Architectures used with the DBLC adder
------------------------------------------------------------

-- Architectures for the DBLC-tree
library ieee;
use ieee.std_logic_1164.all;
architecture INVBLOCK_regular of INVBLOCK is
begin
	GOUT <= not GIN;
end INVBLOCK_regular;

library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK1_regular of BLOCK1 is
begin
	POUT <= not(PIN1 or PIN2);
	GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1_regular;

library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK2_regular of BLOCK2 is
begin
	POUT <= not(PIN1 and PIN2);
	GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2_regular;

library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK1A_regular of BLOCK1A is
begin
	GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1A_regular;

library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK2A_regular of BLOCK2A is
begin
	GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2A_regular;

library ieee;
use ieee.std_logic_1164.all;
architecture XXOR_regular of XXOR1 is
begin
	SUM <= (not (A xor B)) xor GIN;
end XXOR_regular;

library ieee;
use ieee.std_logic_1164.all;
architecture BLOCK0_regular of BLOCK0 is
begin
	POUT <= not(A or B);
	GOUT <= not(A and B);
end BLOCK0_regular;

library ieee;
use ieee.std_logic_1164.all;
architecture PRESTAGE of PRESTAGE_64 is
component BLOCK0
port
(
	A,B,PHI: in std_logic;
	POUT,GOUT: out std_logic
);
end component;
component INVBLOCK
port
(
	GIN,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin  -- PRESTAGE
U1:for I in 0 to 63 generate
	U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: Level 0

library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_0 of DBLC_0_64 is
component INVBLOCK
port
(
	GIN,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

component BLOCK1
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end component;

component BLOCK1A 
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
	U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 64 generate
	U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;

-- The DBLC-tree: Level 1

library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_1 of DBLC_1_64 is