pci_oc.vhd

ARM7的源代码

--         end if;
--        v.wb.cab_o  := '0';
        v.ahbslv.hburst := ahbsi.hburst;
        v.ahbslv.htrans := ahbsi.htrans;
        if ahbsi.haddr(31 downto 16) = "1010000000000000" then -- 0xA000
          v.ahbslv.adr_o  := "0000000000000000" & ahbsi.haddr(15 downto 0);
        else
          v.ahbslv.adr_o  := ahbsi.haddr;          --0xa0010000-0xfffffffc
        end if;
        if (ahbsi.hsel and ahbsi.hready and ahbsi.htrans(1)) = '1' then
--          if ahbsi.hsize = "010" then   --word
            v.ahbslv.hready := '0';
            v.ahbslv_state  := strobe;
            v.ahbslv.we_o   := ahbsi.hwrite;
--          end if; --ahbsi.hsize = word
        end if; --ahbsi.hsel = '1'

      when strobe  =>
        v.ahbslv_state    := respond;
        v.ahbslv.mdat_o   := ahbsi.hwdata;  --write specific
        v.ahbslv.mdat_i    := wbmi.mdat_i;
        vstb_o            := '1';
        v.ahbslv.ack_i    := wbmi.ack_i;
        v.ahbslv.rty_i    := wbmi.rty_i;
        v.ahbslv.hready   := '0';
        if r.ahbslv.hburst = "001" then
          v.wb.cab_o := '1';
--          v.ahbslv.hburst := ahbsi.hburst;
        end if;
        
      when respond =>
        if r.ahbslv.ack_i = '1' then
          v.ahbslv_state    := idle;
          v.ahbslv.hrdata   := r.ahbslv.mdat_i;  --read specific
        elsif r.ahbslv.rty_i = '1' then
          v.ahbslv_state    := rty;
          v.ahbslv.hready   := '0';
          v.ahbslv.hresp    := hresp_retry;
        else
          vstb_o     := '1';              --fix
          v.ahbslv.hready   := '0';
          v.ahbslv.mdat_i   := wbmi.mdat_i;  --read specific
          v.ahbslv.ack_i    := wbmi.ack_i;
          v.ahbslv.rty_i    := wbmi.rty_i;
        end if;
        if (r.wb.cab_o = '1' and ahbsi.htrans(0) = '0') then
          v.wb.cab_o := '0';
        end if;
--        if not r.ahbslv.hburst = "001" then          
--          v.wb.cab_o := '0';
--        end if;

      when rty =>
        v.ahbslv_state  := doreturn;

      when doreturn =>
        v.ahbslv_state  := idle;
        v.ahbslv.hresp  := hresp_okay;

      when others => null;
    end case;

----------------------------------------
----------------------------------------

    v.wb.stb_i := wbsi.stb_i;
    v.wb.we_i := wbsi.we_i;

    v.ahbmst.adr_i     := wbsi.adr_i(31 downto 0);
    v.ahbmst.sdat_i    := wbsi.sdat_i;
    v.rdata            := dmao.rdata;
    vstart             := '0';
    v.ahbmst.ack_o     := '0';
    case r.ahbmst_state is

      when idle =>
        if r.wb.stb_i = '1' then
          v.ahbmst_state := req;
        end if;

      when req  =>
        if dmao.active = '1' and dmao.ready = '1' then
          v.ahbmst.ack_o := '1';
          v.ahbmst_state := respond;
        else
          vstart := '1';
        end if;

      when respond =>
        v.ahbmst_state := idle;

      when others => null;
    end case;

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

--    if apbi.psel = '1' then
--      if apbi.pwrite = '1' then
--        case apbi.paddr(7 downto 0) is
--          when "00000000" =>
--            v.AHB2WBCtrl        := apbi.pwdata;
--          when others       => Null;
--        end case;

--      else
--        case apbi.paddr(3 downto 0) is
--         when "0000" =>
--            vprdata     := r.AHB2WBCtrl;
--          when others       => Null;
--        end case;
--      end if;

--    end if;


    if rst = '0' then
      v.ahbslv_state          := idle;
      v.ahbslv.hresp          := hresp_okay;
      v.ahbslv.hready         := '1';
      v.ahbslv.adr_o          := (others => '0');
      v.ahbslv.hrdata         := (others => '0');
      v.ahbslv.mdat_o         := (others => '0');
      v.ahbslv.mdat_i         := (others => '0');
      v.ahbslv.ack_i          := '0';
      v.ahbslv.rty_i          := '0';
      v.ahbslv.we_o           := '0';

      v.ahbmst_state          := idle;
      v.ahbmst.adr_i          := (others => '0');
      v.ahbmst.ack_o          := '0';
      v.ahbmst.sdat_i         := (others => '0');
      v.rdata                 := (others => '0');

--      v.AHB2WBCtrl            := (others => '0');
      v.wb.cab_o      := '0';

    end if;

    wbmo.adr_o         <= r.ahbslv.adr_o;
--    if is_x(v.ahbslv.mdat_o) then
--      wbmo.mdat_o        <= (others => '0');
--    else
      wbmo.mdat_o        <= v.ahbslv.mdat_o;
--    end if;
    wbmo.we_o          <= r.ahbslv.we_o;
    wbmo.stb_o         <= vstb_o;
    ahbso.hready       <= r.ahbslv.hready;
    ahbso.hresp        <= r.ahbslv.hresp;
    wbmo.cab_o         <= v.wb.cab_o;
--    if is_x(v.ahbslv.hrdata) then
--      ahbso.hrdata       <= (others => '0');
--    else
      ahbso.hrdata       <= v.ahbslv.hrdata;
--    end if;
    ahbso.hsplit       <= (others => '0');
    dmai.address       <= r.ahbmst.adr_i;
--    if is_x(r.ahbmst.sdat_i) then
--      dmai.wdata         <= (others => '0');
--    else
      dmai.wdata         <= r.ahbmst.sdat_i;
--    end if;
    dmai.start         <= vstart;
    dmai.burst         <= '0';
    dmai.write         <= r.wb.we_i;
    dmai.size          <= "10";
    wbso.ack_o         <= r.ahbmst.ack_o;
    wbso.sdat_o        <= r.rdata;
    wbso.rty_o         <= '0';
    apbo.prdata        <= (others => '0');

    pcio.pci_cbe3_en_n <= cbe_en(3);
    pcio.pci_cbe2_en_n <= cbe_en(2);
    pcio.pci_cbe1_en_n <= cbe_en(1);
    pcio.pci_cbe0_en_n <= cbe_en(0);
--    pcio.pci_serr_en_n <= '0';
    pcio.pci_lock_en_n <= '1';
--    pcio.pci_req_en_n  <= '1';

    ocrst <= not rst;
    irq <= '0';

    rin <= v;
  end process comb;

  regs : process(clk)
  begin
    if rising_edge(clk) then
      r <= rin;
    end if;
  end process;

  ahbmst0 : ahbmst port map (rst, clk, dmai, dmao, ahbmi, ahbmo);

  oc : pci_bridge32 port map (

    PCI_CLK_i 		=> pci_clk,
    PCI_AD_oe_o		=> pcio.pci_aden_n,
    PCI_AD_i 		=> pcii.pci_adin,
    PCI_AD_o 		=> pcio.pci_adout,
    PCI_CBE_oe_o 		=> cbe_en,
    PCI_CBE_i 		=> pcii.pci_cbein_n,
    PCI_CBE_o 		=> pcio.pci_cbeout_n,
    PCI_RST_oe_o	=> Open,        --not host
    PCI_RST_i 		=> pcii.pci_rst_in_n,
    PCI_RST_o 		=> Open,        --not host
    PCI_INTA_oe_o	=> pcio.pci_int_en_n,
    PCI_INTA_i 		=> highbits(0),
    PCI_INTA_o 		=> pcio.pci_int_out_n,
    PCI_REQ_oe_o	=> pcio.pci_req_en_n,
    PCI_REQ_o 		=> pcio.pci_req_out_n,
    PCI_GNT_i           => pcii.pci_gnt_in_n,
    PCI_FRAME_oe_o	=> pcio.pci_frame_en_n,
    PCI_FRAME_i		=> pcii.pci_frame_in_n,
    PCI_FRAME_o           => pcio.pci_frame_out_n,
    PCI_IRDY_oe_o	=> pcio.pci_irdy_en_n,
    PCI_IRDY_i 		=> pcii.pci_irdy_in_n,
    PCI_IRDY_o 		=> pcio.pci_irdy_out_n,
    PCI_IDSEL_i		=> pcii.pci_idsel_in,
    PCI_DEVSEL_oe_o	=> pcio.pci_devsel_en_n, --FIX
    PCI_DEVSEL_i	=> pcii.pci_devsel_in_n,
    PCI_DEVSEL_o	=> pcio.pci_devsel_out_n,
    PCI_TRDY_oe_o	=> pcio.pci_trdy_en_n, --FIX
    PCI_TRDY_i 		=> pcii.pci_trdy_in_n,
    PCI_TRDY_o 		=> pcio.pci_trdy_out_n,
    PCI_STOP_oe_o	=> pcio.pci_stop_en_n, --FIX
    PCI_STOP_i 		=> pcii.pci_stop_in_n,
    PCI_STOP_o 		=> pcio.pci_stop_out_n,
    PCI_PAR_oe_o	=> pcio.pci_par_en_n,
    PCI_PAR_i 		=> pcii.pci_par_in,
    PCI_PAR_o 		=> pcio.pci_par_out,
    PCI_PERR_oe_o	=> pcio.pci_perr_en_n,
    PCI_PERR_i 		=> pcii.pci_perr_in_n,
    PCI_PERR_o 		=> pcio.pci_perr_out_n,
    PCI_SERR_oe_o	=> pcio.pci_serr_en_n,
    PCI_SERR_o 		=> pcio.pci_serr_out_n,

     -- SYSCON Signals
     WB_CLK_I       => clk,
     WB_RST_I       => ocrst,
     WB_RST_O       => Open,
     WB_INT_I       => lowbits(0),--negated and propagated to inta_out
     WB_INT_O       => Open,                      --FIX

     -- WISHBONE slave interface
     WBS_ADR_I       => wbmo.adr_o,
     WBS_DAT_I      => wbmo.mdat_o,
     WBS_DAT_O      => wbmi.mdat_i,
     WBS_SEL_I       => highbits(3 downto 0),
     WBS_CYC_I       => highbits(0),
     WBS_STB_I       => wbmo.stb_o,
     WBS_WE_I        => wbmo.we_o,
     WBS_CAB_I       => wbmo.cab_o,
     WBS_ACK_O       => wbmi.ack_i,
     WBS_RTY_O       => wbmi.rty_i,
     WBS_ERR_O       => Open,

     -- WISHBONE master interface
     WBM_ADR_O       => wbsi.adr_i,
     WBM_DAT_I      => wbso.sdat_o,
     WBM_DAT_O      => wbsi.sdat_i,
     WBM_SEL_O       => Open,
     WBM_CYC_O       => Open,
     WBM_STB_O       => wbsi.stb_i,
     WBM_WE_O        => wbsi.we_i,
     WBM_CAB_O       => Open,
     WBM_ACK_I       => wbso.ack_o,
     WBM_RTY_I       => wbso.rty_o,
     WBM_ERR_I       => lowbits(0)
     );

end;