tbench_config.vhd

来自「ARM7的源代码」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use work.tbench_comp.all;

entity tbench_config is
end tbench_config;

architecture behav of tbench_config is
    signal i       : tbench_gen_typ_in;
    signal o       : tbench_gen_typ_out;
begin  
  tb0: tbench_gen port map (i,o);
end behav;