📄 armiu_exstg.vhd
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-- $(/del) t.newcpsr.ex.n := t.cpsr.ex.n; t.newcpsr.ex.z := t.cpsr.ex.z; t.newcpsr.ex.c := r.pctrl.rs.rs_shieftcarryout; when type_arm_sub => -- -- $(del) -- arm@4.1.49: --if ConditionPassed(cond) then -- Rd = Rn - shifter_operand -- if S == 1 and Rd == R15 then -- CPSR = SPSR -- else if S == 1 then -- N Flag = Rd[31] -- Z Flag = if Rd == 0 then 1 else 0 -- C Flag = NOT BorrowFrom(Rn - shifter_operand) -- V Flag = OverflowFrom(Rn - shifter_operand) -- $(/del) t.newcpsr.ex.n := t.cpsr.ex.n; t.newcpsr.ex.z := t.cpsr.ex.z; t.newcpsr.ex.c := not t.cpsr.ex.c; t.newcpsr.ex.v := t.cpsr.ex.v; when type_arm_add => -- -- $(del) -- arm@4.1.3: --if ConditionPassed(cond) then -- Rd = Rn + shifter_operand -- if S == 1 and Rd == R15 then -- CPSR = SPSR -- else if S == 1 then -- N Flag = Rd[31] -- Z Flag = if Rd == 0 then 1 else 0 -- C Flag = CarryFrom(Rn + shifter_operand) -- V Flag = OverflowFrom(Rn + shifter_operand) -- $(/del) t.newcpsr.ex.n := t.cpsr.ex.n; t.newcpsr.ex.z := t.cpsr.ex.z; t.newcpsr.ex.c := t.cpsr.ex.c; t.newcpsr.ex.v := t.cpsr.ex.v; when type_arm_rsb => -- Reverse Subtract -- $(del) -- arm@4.1.36: --if ConditionPassed(cond) then -- Rd = shifter_operand - Rn -- if S == 1 and Rd == R15 then -- CPSR = SPSR -- else if S == 1 then -- N Flag = Rd[31] -- Z Flag = if Rd == 0 then 1 else 0 -- C Flag = NOT BorrowFrom(shifter_operand - Rn) -- V Flag = OverflowFrom(shifter_operand - Rn) -- $(/del) t.newcpsr.ex.n := t.cpsr.ex.n; t.newcpsr.ex.z := t.cpsr.ex.z; t.newcpsr.ex.c := not t.cpsr.ex.c; t.newcpsr.ex.v := t.cpsr.ex.v; when type_arm_adc => -- Add with Carry -- $(del) -- arm@4.1.2: --if ConditionPassed(cond) then -- Rd = Rn + shifter_operand + C Flag --if S == 1 and Rd == R15 then -- CPSR = SPSR --else if S == 1 then -- N Flag = Rd[31] -- Z Flag = if Rd == 0 then 1 else 0 -- C Flag = CarryFrom(Rn + shifter_operand + C Flag) -- V Flag = OverflowFrom(Rn + shifter_operand + C Flag) -- $(/del) t.newcpsr.ex.n := t.cpsr.ex.n; t.newcpsr.ex.z := t.cpsr.ex.z; t.newcpsr.ex.c := t.cpsr.ex.c; t.newcpsr.ex.v := t.cpsr.ex.v; when type_arm_sbc => -- Subtract with Carry -- $(del) -- arm@4.1.38: --if ConditionPassed(cond) then -- Rd = Rn - shifter_operand - NOT(C Flag) -- if S == 1 and Rd == R15 then -- CPSR = SPSR -- else if S == 1 then -- N Flag = Rd[31] -- Z Flag = if Rd == 0 then 1 else 0 -- C Flag = NOT BorrowFrom(Rn - shifter_operand - NOT(C Flag)) -- V Flag = OverflowFrom(Rn - shifter_operand - NOT(C Flag)) -- $(/del) t.newcpsr.ex.n := t.cpsr.ex.n; t.newcpsr.ex.z := t.cpsr.ex.z; t.newcpsr.ex.c := not t.cpsr.ex.c; t.newcpsr.ex.v := t.cpsr.ex.v; when type_arm_rsc => -- Reverse Subtract with Carry -- $(del) -- arm@4.1.37: --if ConditionPassed(cond) then -- Rd = shifter_operand - Rn - NOT(C Flag) -- if S == 1 and Rd == R15 then -- CPSR = SPSR -- else if S == 1 then -- N Flag = Rd[31] -- Z Flag = if Rd == 0 then 1 else 0 -- C Flag = NOT BorrowFrom(shifter_operand - Rn - NOT(C Flag)) -- V Flag = OverflowFrom(shifter_operand - Rn - NOT(C Flag)) -- $(/del) t.newcpsr.ex.n := t.cpsr.ex.n; t.newcpsr.ex.z := t.cpsr.ex.z; t.newcpsr.ex.c := not t.cpsr.ex.c; t.newcpsr.ex.v := t.cpsr.ex.v; when type_arm_strhb => when type_arm_str1 | type_arm_str2 | type_arm_str3 => when type_arm_ldrhb => when type_arm_ldr1 => null; when type_arm_undefined => null; when type_arm_stm => null; when type_arm_ldm => null; when type_arm_b => null; when type_arm_swi => null; when others => null; end case; -- reset if ( rst = '0' ) then v.cpsr.ex.n := '0'; v.cpsr.ex.z := '0'; v.cpsr.ex.c := '0'; v.cpsr.ex.v := '0'; v.cpsr.wr.i := '0'; v.cpsr.wr.f := '0'; v.cpsr.wr.t := '0'; v.cpsr.wr.mode := APM_SVC; -- change end if; -- pipeline propagation t.o.pctrl_r := r.pctrl; t.o.toDM_pctrl_v := v.pctrl; -- pipeline flush if not (t.commit = '1') then t.o.toDM_pctrl_v.valid := '0'; end if; t.o.cpsr_r := r.cpsr; t.o.alures_v := t.result; t.o.toIM_branch_v := '0'; t.o.flush_v := '0'; case r.pctrl.ex.exop_data_src is when apc_datasrc_aluout => t.o.toDM_pctrl_v.data1 := t.result;-- todo: check obsolete apd_datasrc_op1 --when apc_datasrc_op1 => t.o.toDM_pctrl_v.data1 := r.pctrl.data1; when apc_datasrc_buf => t.o.toDM_pctrl_v.data1 := r.buf; when apc_datasrc_none => when others => null; end case; if apc_is_strdata(r.pctrl) then case r.pctrl.me.meop_param.size is when lmd_byte => t.o.toDM_pctrl_v.data2 := r.pctrl.data2(7 downto 0) & r.pctrl.data2(7 downto 0) & r.pctrl.data2(7 downto 0) & r.pctrl.data2(7 downto 0); when lmd_half => t.o.toDM_pctrl_v.data2 := r.pctrl.data2(15 downto 0) & r.pctrl.data2(15 downto 0); when others => end case; end if; case r.pctrl.ex.exop_buf_src is when apc_exbufsrc_aluout => v.buf := t.result; when apc_exbufsrc_op1 => v.buf := r.pctrl.data1; when apc_exbufsrc_none => when others => null; end case; -- branching if apc_is_valid(r.pctrl) then if apc_is_branch(r.pctrl) then t.o.flush_v := '1'; if not apc_is_memload(r.pctrl) then if t.commit = '1' then t.o.toIM_branch_v := '1'; end if; end if; end if; end if; if apc_is_valid(r.pctrl) then if r.pctrl.wr.wrop_trap.trap = '1' then t.o.flush_v := '1'; case r.pctrl.wr.wrop_trap.traptype is when apm_trap_reset => -- $(del)-- R14_svc = UNPREDICTABLE value-- SPSR_svc = UNPREDICTABLE value-- CPSR[4:0] = 0b10011 /* Enter Supervisor mode */-- CPSR[5] = 0 /* Execute in ARM state */-- CPSR[6] = 1 /* Disable fast interrupts */-- CPSR[7] = 1 /* Disable normal interrupts */-- if high vectors configured then-- PC = 0xFFFF0000-- else-- PC = 0x00000000-- $(/del) when apm_trap_undef =>-- $(del)-- R14_und = address of next instruction after the undefined instruction-- SPSR_und = CPSR-- CPSR[4:0] = 0b11011 /* Enter Undefined mode */-- CPSR[5] = 0 /* Execute in ARM state */-- /* CPSR[6] is unchanged */-- CPSR[7] = 1 /* Disable normal interrupts */-- if high vectors configured then-- PC = 0xFFFF0004-- else-- PC = 0x00000004-- $(/del) when apm_trap_swi =>-- $(del)-- R14_svc = address of next instruction after the SWI instruction-- SPSR_svc = CPSR-- CPSR[4:0] = 0b10011 /* Enter Supervisor mode */-- CPSR[5] = 0 /* Execute in ARM state */-- /* CPSR[6] is unchanged */-- CPSR[7] = 1 /* Disable normal interrupts */-- if high vectors configured then-- PC = 0xFFFF0008-- else-- PC = 0x00000008-- $(/del) when apm_trap_prefch =>-- $(del)-- R14_abt = address of the aborted instruction + 4-- SPSR_abt = CPSR-- CPSR[4:0] = 0b10111 /* Enter Abort mode */-- CPSR[5] = 0 /* Execute in ARM state */-- /* CPSR[6] is unchanged */-- CPSR[7] = 1 /* Disable normal interrupts */-- if high vectors configured then-- PC = 0xFFFF000C-- else-- PC = 0x0000000C-- $(/del) when apm_trap_dabort =>-- $(del)-- R14_abt = address of the aborted instruction + 8-- SPSR_abt = CPSR-- CPSR[4:0] = 0b10111 /* Enter Abort mode */-- CPSR[5] = 0 /* Execute in ARM state */-- /* CPSR[6] is unchanged */-- CPSR[7] = 1 /* Disable normal interrupts */-- if high vectors configured then-- PC = 0xFFFF0010-- else-- PC = 0x00000010-- $(/del) when apm_trap_irq =>-- $(del)-- R14_irq = address of next instruction to be executed + 4-- SPSR_irq = CPSR-- CPSR[4:0] = 0b10010 /* Enter IRQ mode */-- CPSR[5] = 0 /* Execute in ARM state */-- /* CPSR[6] is unchanged */-- CPSR[7] = 1 /* Disable normal interrupts */-- if high vectors configured then-- PC = 0xFFFF0018-- else-- PC = 0x00000018-- $(/del) when apm_trap_fiq =>-- $(del)-- R14_fiq = address of next instruction to be executed + 4-- SPSR_fiq = CPSR-- CPSR[4:0] = 0b10001 /* Enter FIQ mode */-- CPSR[5] = 0 /* Execute in ARM state */-- CPSR[6] = 1 /* Disable fast interrupts */-- CPSR[7] = 1 /* Disable normal interrupts */-- if high vectors configured then-- PC = 0xFFFF001C-- else-- PC = 0x0000001C-- $(/del) when others => end case; end if; end if; t.o.toDM_pctrl_v.ex.ex_cpsr := r.cpsr; if i.pstate.hold_r.hold = '0' then v.pctrl := i.fromRS_pctrl_v; if apc_is_valid(r.pctrl) then if t.commit = '1' then v.cpsr := t.newcpsr; end if; end if; if i.fromWR_cpsrset_v = '1' then v.cpsr := i.fromWR_cpsr_v; end if; end if; t.o.cpsr_v := v.cpsr; c <= v; o <= t.o; -- pragma translate_off vdbg := rdbg; vdbg.dbg := t; vdbg.dbg.dbgaluop := adg_todbgaluop(r.pctrl.ex.exop_aluop); cdbg <= vdbg; -- pragma translate_on end process p0; pregs : process (clk, c) begin if rising_edge(clk) then r <= c; -- pragma translate_off rdbg <= cdbg; -- pragma translate_on end if; end process; end rtl;
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