armiu_drstg.vhd

ARM7的源代码

    t.micro.pctrl.rs.rsop_sdir := ash_sdir_snone;
    t.micro.pctrl.rs.rs_shieftcarryout := '0';
    t.micro.pctrl.ex.exop_aluop := (others => '0');
    t.micro.pctrl.ex.exop_data_src := apc_datasrc_aluout;
    t.micro.pctrl.ex.exop_buf_src := apc_exbufsrc_none;
    t.micro.pctrl.ex.exop_setcpsr := '0';
    t.micro.pctrl.ex.ex_cpsr.ex.n := '0';
    t.micro.pctrl.ex.ex_cpsr.ex.z := '0';
    t.micro.pctrl.ex.ex_cpsr.ex.c := '0';
    t.micro.pctrl.ex.ex_cpsr.ex.v := '0';
    t.micro.pctrl.ex.ex_cpsr.wr.i := '0';
    t.micro.pctrl.ex.ex_cpsr.wr.f := '0';
    t.micro.pctrl.ex.ex_cpsr.wr.t := '0';
    t.micro.pctrl.ex.ex_cpsr.wr.mode := (others => '0');
    t.micro.pctrl.dm.dummy := '0';
    t.micro.pctrl.me.meop_enable := '0';
    t.micro.pctrl.me.meop_param.size := lmd_word;
    t.micro.pctrl.me.meop_param.read := '0';
    t.micro.pctrl.me.meop_param.lock := '0';
    t.micro.pctrl.me.meop_param.writedata := '0';
    t.micro.pctrl.me.meop_param.addrin := '0';
    t.micro.pctrl.me.meop_param.signed := '0';
    t.micro.pctrl.me.mexc := '0';
    t.micro.pctrl.wr.wrop_rd := (others => '0');
    t.micro.pctrl.wr.wrop_rdvalid := '0';
    t.micro.pctrl.wr.wrop_setspsr := '0';
    t.micro.pctrl.wr.wrop_trap.traptype := apm_trap_reset;
    t.micro.pctrl.wr.wrop_trap.trap := '0';
    t.micro.pctrl.data1 := (others => '0');
    t.micro.pctrl.data2 := (others => '0');
    t.micro.valid := '0';
    t.micro.r1 := (others => '0');
    t.micro.r2 := (others => '0');
    t.micro.r1_valid := '0';
    t.micro.r2_valid := '0';
    t.am.DAPRAM_typ := ade_DAPRAM_simm;
    t.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
    t.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
    t.am.LDSTAMxLSV4AM_pos := ade_pre;
    t.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
    t.am.LDSTAMxLSV4AM_uacc := '0';
    t.am.LDSTAMxLSV4AM_wb := '0';
    t.r1_src := acm_none;
    t.r2_src := acm_none;
    t.rd_src := acm_rdnone;
    t.rn := (others => '0');
    t.rm := (others => '0');
    t.rd := (others => '0');
    t.rs := (others => '0');
    t.rlink := (others => '0');
    t.rpc := (others => '0');
    t.nr := (others => '0');
    t.nr_i := 0;
    t.nr_c := '0';
    t.startoff := (others => '0');
    t.endoff := (others => '0');
    t.incval := (others => '0');
    t.m1 := (others => '0');
    t.m2 := (others => '0');
    t.md := (others => '0');
    t.m1_valid := '0';
    t.m2_valid := '0';
    t.rr1 := (others => '0');
    t.rr2 := (others => '0');
    t.rrd := (others => '0');
    t.rmode := (others => '0');

    -- $(/init-automatically-generated-for-synthesis:(t:armiu_drstg_tmp_type))
    
    v := r;
    t.commit := not i.flush_v;

    t.insn := i.fromDE_insn_r.insn.insn;
    t.am := i.fromDE_insn_r.insn.am;
    t.rn := t.insn(ADE_RN_U downto ADE_RN_D);
    t.rm := t.insn(ADE_RM_U downto ADE_RM_D);
    t.rs := t.insn(ADE_SREG_U downto ADE_SREG_D);
    t.rd := t.insn(ADE_RD_U downto ADE_RD_D);
    t.rlink := APM_REG_LINK;
    t.r1_src    := acm_none;
    t.r2_src    := acm_none;
    t.rmode := i.pstate.fromEX_cpsr_r.wr.mode;
    t.m1 := t.rd;
    t.m2 := t.rd;
    t.md := t.rd;
    t.nr_c := '1';
    
    -- cmd lm, sm:
    t.nr := als_getnextpos(t.insn, r.reglist);
    t.nr_i := lin_convint(t.nr);

    als_offsets (t.insn, t.startoff, t.endoff, t.incval );
    
    t.mem := '0';
    if apc_is_mem(i.pstate.fromRR_pctrl_r) or
       apc_is_mem(i.pstate.fromRS_pctrl_r) or
       apc_is_mem(i.pstate.fromEX_pctrl_r) or
       apc_is_mem(i.pstate.fromDM_pctrl_r) or
       apc_is_mem(i.pstate.fromME_pctrl_r) or
       apc_is_mem(i.pstate.fromWR_pctrl_r) then
      t.mem := '1';
    end if;

    t.ctrlo.nextinsn := '1';
    t.ctrlo.nextcnt := '1';
    t.ctrlo.hold := '0';
    
    t.ctrli.cnt := r.cnt;
    t.ctrli.insn := i.fromDE_insn_r.insn;
    t.ctrli.ctrlo := t.ctrlo;

    t.pctrl.insn := i.fromDE_insn_r.insn;
    t.pctrl.ex.exop_aluop := i.fromDE_insn_r.insn.insn(ADE_OP_U downto ADE_OP_D);
    t.pctrl_bypass := t.pctrl;
    
    case i.fromDE_insn_r.insn.decinsn is
      when type_arm_invalid => 
      when type_arm_nop =>
        
-------------------------------------------------------------------------------
        
      when type_arm_mrs | 
           type_arm_msr =>

        t.cmdsri.ctrli := t.ctrli;
        t.cmdsri.deid := i.fromDE_insn_r.insn.id;
        t.cmdsri.exid := i.pstate.fromEX_pctrl_r.insn.id;
        t.cmdsri.exvalid := i.pstate.fromEX_pctrl_r.valid;
        t.cmdsri.wrid := i.pstate.fromWR_pctrl_r.insn.id;
        t.cmdsri.wrvalid := i.pstate.fromWR_pctrl_r.valid;
        t.ctrlo := cmdsro.ctrlo;
        
        t.r1_src := acm_none;
        t.r2_src := cmdsro.r2_src;
        t.rd_src := cmdsro.rd_src;
        
         -- rsstg: 
        t.pctrl.rs.rsop_op1_src := apc_opsrc_none;
        t.pctrl.rs.rsop_op2_src := cmdsro.rsop_op2_src;
        t.pctrl.rs.rsop_styp := cmdsro.rsop_styp;
        t.pctrl.rs.rsop_sdir := cmdsro.rsop_sdir;

        -- exstg:
        t.pctrl.ex.exop_setcpsr := cmdsro.exop_setcpsr;
        
-------------------------------------------------------------------------------
        
      when type_arm_bx => 
      when type_arm_mul => 
      when type_arm_mla => 
      when type_arm_sumull => 
      when type_arm_sumlal =>
        
-------------------------------------------------------------------------------
        
      when type_arm_teq |  
           type_arm_cmn |  
           type_arm_tst |  
           type_arm_cmp |
           type_arm_and |
           type_arm_sub |
           type_arm_eor |
           type_arm_rsb |
           type_arm_add |
           type_arm_orr |
           type_arm_bic |
           type_arm_mov |
           type_arm_mvn | 
           type_arm_sbc |  
           type_arm_adc |  
           type_arm_rsc =>
        
        t.cmdali.ctrli := t.ctrli;
        
        t.ctrlo := cmdalo.ctrlo;
        
        -- rrstg
        t.r1_src := cmdalo.r1_src;      -- (micro.r1)
        t.r2_src := cmdalo.r2_src;      -- (micro.r2)
        t.rd_src := cmdalo.rd_src;      -- (pctrl.wr.wrop_rd)
  
        -- rsstg:
        t.pctrl.rs.rsop_op1_src := cmdalo.rsop_op1_src; -- EXSTG operand1 source 
        t.pctrl.rs.rsop_op2_src := cmdalo.rsop_op2_src; -- EXSTG operand2 source 
        t.pctrl.rs.rsop_buf2_src := cmdalo.rsop_buf2_src; -- RSSTG buffer1 source
        t.pctrl.rs.rsop_styp := ash_styp_none;
        t.pctrl.rs.rsop_sdir := t.am.DAPRAMxLDSTAM_sdir;
        case t.am.DAPRAM_typ is
          when ade_DAPRAM_immrot => t.pctrl.rs.rsop_styp := ash_styp_immrot;
          when ade_DAPRAM_simm   => t.pctrl.rs.rsop_styp := ash_styp_simm;
          when ade_DAPRAM_sreg   => t.pctrl.rs.rsop_styp := ash_styp_sreg;
          when others => null;
        end case;
        
        t.pctrl.ex.exop_setcpsr := t.insn(ADE_SETCPSR_C);
        
-------------------------------------------------------------------------------
        
      when type_arm_str1 | type_arm_str2 | type_arm_str3 |
           type_arm_strhb =>

        t.cmdsti.ctrli := t.ctrli;
        
        t.ctrlo := cmdsto.ctrlo;
        
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdsto.ctrlmemo );
        
        case i.fromDE_insn_r.insn.decinsn is
          when type_arm_str1 |
               type_arm_str2 |
               type_arm_str3  =>
            als_LDSTAM_init_size(t.insn, t.pctrl);
          when others =>
            als_LSV4AM_init_size(t.insn, t.pctrl);
        end case;

        als_LDSTAMxLSV4AM_init_addsub(t.insn, t.pctrl);
        
        t.pctrl.rs.rsop_styp := cmdsto.rsop_styp; -- RSSTG shieft op 
        t.pctrl.rs.rsop_sdir := cmdsto.rsop_sdir; -- RSSTG shieft dir 
      
-------------------------------------------------------------------------------
        
      when type_arm_ldr1 |
           type_arm_ldrhb =>
        
        t.cmdldi.ctrli := t.ctrli;
        
        t.ctrlo := cmdldo.ctrlo;
        
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdldo.ctrlmemo );
        
        case i.fromDE_insn_r.insn.decinsn is
          when type_arm_ldr1 =>
            als_LDSTAM_init_size(t.insn, t.pctrl);
          when others =>
            als_LSV4AM_init_size(t.insn, t.pctrl);
        end case;
        
        als_LDSTAMxLSV4AM_init_addsub(t.insn, t.pctrl);
        
        t.pctrl.rs.rsop_styp := cmdldo.rsop_styp; -- RSSTG shieft op 
        t.pctrl.rs.rsop_sdir := cmdldo.rsop_sdir; -- RSSTG shieft dir 
        
-------------------------------------------------------------------------------
        
      when type_arm_stm =>

        t.cmdsmi.ctrli := t.ctrli;
        
        t.cmdsmi.ctrlmulti.ival := t.incval;
        t.cmdsmi.ctrlmulti.soff := t.startoff;
        t.cmdsmi.ctrlmulti.eoff := t.endoff;
        t.cmdsmi.ctrlmulti.reglist := r.reglist;
        t.cmdsmi.ctrlmulti.mem := t.mem;
        t.cmdsmi.ctrlmulti.dabort := i.fromWR_dabort_v;
        
        t.ctrlo := cmdsmo.ctrlo;
        
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdsmo.ctrlmemo );
        
        t.pctrl.ex.exop_aluop := ADE_OP_ADD;
        
        t.m1 := t.nr;               -- acm_local
        t.nr_c := r.cnt(0);         -- every second cycle
      
-------------------------------------------------------------------------------
        
      when type_arm_ldm =>
        
        t.cmdlmi.ctrli := t.ctrli;
        
        t.cmdlmi.ctrlmulti.ival := t.incval;
        t.cmdlmi.ctrlmulti.soff := t.startoff;
        t.cmdlmi.ctrlmulti.eoff := t.endoff;
        t.cmdlmi.ctrlmulti.reglist := r.reglist;
        t.cmdlmi.ctrlmulti.mem := t.mem;
        t.cmdlmi.ctrlmulti.dabort := i.fromWR_dabort_v;
        
        t.ctrlo := cmdlmo.ctrlo;
        
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdlmo.ctrlmemo );
        
        t.pctrl.ex.exop_aluop := ADE_OP_ADD;
        
        t.md := t.nr;                   -- acm_rdlocal
        
-------------------------------------------------------------------------------
        
      when type_arm_b =>

        t.ctrlo := cmdblo.ctrlo;

        t.r1_src := cmdblo.r1_src;
        t.r2_src := cmdblo.r2_src;
        t.rd_src := cmdblo.rd_src;
        t.pctrl.data2 := cmdblo.data2;
        
        -- rsstg:
        t.pctrl.rs.rsop_op2_src := cmdblo.rsop_op2_src;
        -- exstg:
        t.pctrl.ex.exop_aluop := ADE_OP_ADD;
        
        t.m1 := APM_REG_PC;            -- acm_local
      
-------------------------------------------------------------------------------
        
      when type_arm_swp =>
        
        t.cmdswi.ctrli := t.ctrli;

        t.ctrlo := cmdswo.ctrlo;
        
        t.pctrl.ex.exop_aluop := ADE_OP_ORR;
        
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdswo.ctrlmemo );
        
-------------------------------------------------------------------------------
        
      when type_arm_stc =>
        t.cmdcsi.ctrli := t.ctrli;

        t.cmdcsi.fromCP_busy := i.fromCPDE_busy;
        t.cmdcsi.fromCP_last := i.fromCPDE_last;
        t.ctrlo := cmdcso.ctrlo;
        
      when type_arm_ldc =>
        t.cmdcli.ctrli := t.ctrli;